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IC Internal Diagram
PRELIMINARY DATA SHEET
2. Functional Description of the MAS 3507D
2.1. DSP Core
The hardware of the MAS 3507D consists of a high
performance RISC Digital Signal Processor (DSP) and
appropriate interfaces (see Fig. 2–1). The internal pro-
cessor works with a memory word length of 20 bits
and an extended range of 32 bits in its accumulators.
The instruction set of the DSP is highly optimized for
audio data compression and decompression. Thus,
only very small areas of internal RAM and ROM are
required. All data input and output actions are based
on a 'non cycle stealing' background DMA that does
not cause any computational overhead.
MPEG Bit Stream
Digital Audio Output
Fig. 2–1: Block diagram of the MPEG Decoder in serial input mode
Micronas
Samsung Electronics
Sync
Volume
MPEG
Tone
Decoder
Control
PIO
Status
Start-up Config.
2.2. Firmware (Internal Program ROM)
A valid MPEG 1/2/2.5 layer 2/3 data signal is taken as
input. The signal lines are a clock line SIC and the data
line SID. The MPEG decoder performs the audio
decoding. The steps for decoding are
– synchronization,
– side information extraction,
– audio data decoding,
– ancillary data extraction, and
– volume and tone control.
For the supported bit rates and sample rates, see
Table 3–12 on page 32. Frame synchronization and
CRC-error signals are provided at the output pins of
the MAS 3507D in serial input mode.
Ancillary
Data
to µC
Decoder
Status
Config. Reg.
MAS 3507D
7
7-13
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