JVC LT-42DA9BN Service Manual page 48

MPEG PWB CIRCUIT DIAGRAM (3/18) [CI2000/CI2002]
5
MPEG PWB
(5/18)
PR1 OPEN-000*4
PR4 OPEN-000*4
TS_DATA[7..0]
TS_DATA0
1
TS_DATA1
2
TS_DATA2
3
TS_DATA3
4
TS_DATA4
1
TS_DATA5
2
TS_DATA6
3
D
TS_DATA7
4
TS_STR OPEN-000/1005
R5
TS_STR
TS_VLD R7 OPEN-000/1005
TS_VLD
TS_CLK R8 OPEN-000/1005
TS_CLK
Option for Free to Air
CI1_MDO[7..0]
CI1_MDO0
CI1_MDO1
CI1_MDO2
CI1_MDO3
CI1_MDO4
CI1_MDO5
CI1_MDO6
CI1_MDO7
MPEG PWB(4/18)
CI1_STRO
CI1_STRO
CI1_VLDO
CI1_VLDO
CI1_CLKO
CI1_CLKO
CI1_CD1
C CI1_CD1
CI1_CD2
CI1_CD2
CI1_WAIT
CI1_WAIT
CI1_IRQ
CI1_IRQ
R13
472/1005
R14
OPEN-472/1005
R15
OPEN-000/1005
CPU_WAIT
B
nDTACK
R16
472/1005
+3V3
Control signal for host interfacing
nCI2002_CS
MPEG PWB(9/18) nCI2002_CS
HOE
MPEG PWB(9/18),(11/18)
F_OE
nRST
MPEG PWB(9/18),(10/18)
nRST
A
CI_IRQ
MPEG PWB(9/18) CI_IRQ
CLK27M_CI
MPEG PWB(10/18)
CLK27M_CI
CPU_WAIT
MPEG PWB(9/18)
CPU_WAIT
HWE
MPEG PWB
F_WE/DQM0
(9/18),(11/18),(12/18)
All locations are from 1 to 39 in this page
5
4
+5V
CAD0
8
CAD1
7
CAD2
6
CAD3
5
CAD4
8
CAD5
R1
7
CAD6
000
6
CAD7
5
CASTR
CAVLD
CACLK
CI1_MDO3
1
TDO3_A
CI1_MDO4
2
TDO4_A
CI1_MDO5
3
TDO5_A
CI1_MDO6
4
TDO6_A
CI1_MDO7
5
TDO7_A
6
GND
7
ADDR10_B
8
/OE_B
9
/CE_B
10
D7_B
11
D6_B
12
D5_B
13
D4_B
14
D3_B
15
+3V3 3.3V
CI1_D3
16
D3_A
CI1_D4
17
D4_A
CI1_D5
18
D5_A
CI1_D6
19
D6_A
CI1_D7
20
D7_A
CI1_CE
21
/CE_A
CI1_A10
22
ADDR10_A
CI1_OE
23
/OE_A
24
GND
CLK27M_CI
25
27CLK
nRST
26
RESET
ADDR16
27
SEL1
+3V3
ADDR15
28
SEL0
ADDR3
29
HA2
ADDR2
30
HA1
ADDR1
31
HA0
nCI2002_CS
32
/HCE
HWE
33
/HWE
HOE
34
/HOE
CI_IRQ
35
/HIRQ
ACK
36
ACK
DTACK
37
DTACK
DATA0
38
HD0
DATA1
39
HD1
DATA2
40
HD2
R17 OPEN-000/1005
from CPU_OE
from Reset 3
GND
nDTACK 4
Y
to CPU_PIO
2
A
from CPU CLOCK
5
+3V3
VCC
to CPU_WAIT 1
NC
from CPU_BE0 C5 U2
104p/1005 ELM7S04B
4
(No.YA608<Rev.001>)2-55
3
+3V3
R2
OPEN-000
C1
104p/1005
120
TOA_STR
119
TOA_VLD
118
GND
117
TI_CLK
116
TI_STR
115
TI_VLD
114
TI_D0
113
TI_D1
112
TI_D2
111
TI_D3
110
TI_D4
109
TI_D5
108
TI_D6
107
TI_D7
106
D0_B
105
D1_B
104
U1
D2_B
103
/WAIT_A
102
/WAIT_B
CI2000PB 101
D0_A
100
D1_A
99
D2_A
98
RESET_B
97
+3.3V
96
ADDR7_B
95
ADDR6_B
94
ADDR5_B
93
ADDR4_B
92
ADDR3_B
91
ADDR2_B
90
ADDR1_B
89
ADDR0_B
88
GND
87
ADDR0_A
86
ADDR1_A
85
ADDR2_A
84
ADDR3_A
83
ADDR4_A
82
ADDR5_A
81
ADDR6_A
C2
104p/1005
R18 R19
000 OPEN-000
DTACK 104p/1005
+5V +3V3
3
2-56(No.YA608<Rev.001>)
2
PR2
PR3
CI1_A[11..0]
CI1_A11 CI1_TDI0
1
CI1_A10 CI1_TDI1
2
CI1_A9 CI1_TDI2
3
CI1_A8 CI1_TDI3
4
CI1_A7 CI1_TDI4
1
CI1_A6 CI1_TDI5
2
MPEG
CI1_A5 CI1_TDI6
3
PWB
CI1_A4 CI1_TDI7
4
(4/18)
CI1_A3
CI1_A2 CI1_TSTRI
R3
CI1_A1 CI1_TVLDI
R4
CI1_A0 CI1_TCLKI
R6
CI1_D[7..0]
CI1_D7
CI1_D6
CI1_D5
CI1_D4 L1
CI1_D3 BLM18AG601SN1D
CI1_D2
CI1_D1
CI1_D0
CI1_STRO
CI1_VLDO
TS_CLK
PR5 470*4
TS_STR
PR6 470*4
TS_VLD TO_D0 CAD0
1 8
TS_DATA0 TO_D1 CAD1
2 7
TS_DATA1 TO_D2 CAD2
3 6
TS_DATA2 TO_D3 CAD3
4 5
TS_DATA3 TO_D4 CAD4
1 8
TS_DATA4 TO_D5 CAD5
2 7
TS_DATA5 TO_D6 CAD6
3 6
TS_DATA6 TO_D7 CAD7
4 5
TS_DATA7
TO_STR R9 470/1005 CASTR
R12 TO_VLD R10 470/1005 CAVLD
TO_CLK CACLK
103/1005 R11 470/1005
+5V
CI1_WAIT
CI1_D0
CI1_D1
CI1_D2 Option for CI
+3V3
CI1_CE
CI1_CE
CI1_OE
CI1_OE
CI1_WE
CI1_WE
CI1_A0 CI1_IOWR
CI1_IOWR
MPEG PWB(4/18)
CI1_A1 CI1_IORD
CI1_IORD
CI1_A2
CI1_A3 CAS1RST
CAS1RST
CI1_A4 CAS1PWR
CAS1PWR
CI1_A5
CI1_A6
MPEG PWB(9/18),(11/18),(12/18),(15/18)
+3V3
MPEG PWB ASS'Y (3/18)
C4
C3
104p/1005
[CI2000/CI2002]
HU-71200005
2
1
470*4
470*4
CI1_MDI[7..0]
CI1_MDI0
8
CI1_MDI1
7
CI1_MDI2
6
CI1_MDI3
5
CI1_MDI4
8
MPEG
CI1_MDI5
7
CI1_MDI6 PWB
6
CI1_MDI7 (4/18)
5
D
CI1_STRI
470/1005
CI1_STRI
CI1_VLDI
470/1005
CI1_VLDI
CI1_CLKI
470/1005
CI1_CLKI
CAD[7..0]
C
MPEG PWB(9/18)
CASTR
CAVLD
CACLK
MPEG PWB(9/18),(11/18),(12/18),(15/18)
DATA[7..0]
DATA0
DATA1
DATA2
DATA3
DATA4
B
DATA5
DATA6
DATA7
ADDR16
ADDR16
ADDR15
ADDR15
ADDR3
ADDR3
ADDR2
ADDR2
ADDR1
ADDR1
A
1
lt-19db9bd_mpeg-02_0520_2/21_0.0