3DQDVRQLF Contents CIRCUIT DESCRIPTION ........................... 3 ..........................3 MALL SIGNAL PART 1.1.1 Tuner and IF output Tuner: ......................3 1.1.2 Vision IF ............................3 1.1.3 Sound ............................... 8 1.1.4 Horizontal and vertical synchronization ..................10 1.1.5 Luminance and chrominance signal processing ................13 1.1.6 Color Decoder ..........................
3DQDVRQLF 1 Circuit Description 1.1 Small signal part 1.1.1 Tuner and IF output Tuner: Type TV standard Channel coverage 38.9 MHz VHF_L : CH E2 -- CH S7 DT5-BF15P L/L’ 38.9 MHz VHF_H : CH S8 -- CH S36 (DAEWOO) 38.9 MHz UHF : CH S37 -- CH E69 The RF tuner selects the picture and sound signals of the desired station by converting the RF signal...
3DQDVRQLF * IF-amplifier The IF-amplifier has symmetrical inputs and consists of three AC coupled differential gain stages with AGC function. Due to the AC coupling, biasing is simple so that cascades can be used and no DC feedback is necessary. The gain control range of the IF amplifier is 64dB minimal. The input sensitivity for AGC onset is 70 mV typical.
3DQDVRQLF * AGC An AGC system controls the IF amplifier gain such that the video output amplitude is constant. The demodulated video signal is supplied, via a low pass filter, to an AGC detector with external decoupling capacitor. The AGC detector voltage controls directly the IF gain stages. Negative/positive modulation: For optimal AGC behavior the charge and discharge current of the AGC are chosen so that both, a relative fast AGC, as well a low tilt are possible for positive and negative modulated signals with the...
3DQDVRQLF Original video signal Demodulated signal on video output with/without ref. pulse Not optimal behaviour Optimal behaviour 100% 100% pulse pulse 100% Ref pulse 100%, luma 50% Top white AGC Top white AGC only 100% 100% Ref pulse, top white<100% Black clamp AGC Fig 3: Top white and black clamp AGC The Fig 3 “b”...
3DQDVRQLF 1.1.3 Sound See also the related block diagram as well as the diagrams at the end of the report. The main functions are: * Limiter * PLL-Demodulator * Pre-amplifier and mute * Audio switch * Volume controlled amplifier These functions will be described next. * Limiter The sound carrier signal is supplied to this limiter input via an external bandpass filter.
3DQDVRQLF 1.1.4 Horizontal and vertical synchronization See also the related block diagram as well as the diagrams at the end of the report. The main functions are: * Horizontal sync separator * Horizontal oscillator and calibration system * PHI-1 detector * PHI-2 detector and sandcastle generation * Horizontal output with slow start/stop facility * Coincidence detector...
3DQDVRQLF * H-output and slow start/stop The horizontal output is the driver pin for the line deflection. It is an open collector output. Under normal operation condition the duty cycle of the output pulse is 45% off (Hout = high) / 55% on (Hout = low).
3DQDVRQLF 3. Standard TV-norm: divider ratio 525 (60Hz) or 625 (50Hz) When the system is switched to the narrow window (standard mode) it is checked whether the incoming vertical sync pulses are according to the TV norm, if so IVW=1. When 15 standard TV-norms are counted the divider system is switched to the standard divider ratio mode.
3DQDVRQLF 1.1.5 Luminance and chrominance signal processing * Chrominance signal processing For chroma signal processing, the selected signal is supplied to both the PAL/NTSC chroma bandpass filter and the SECAM cloche filter via a variable gain amplifier which is controlled by ACC and ACL detection circuits.
3DQDVRQLF 1.1.6 Color Decoder See also the related block diagram as well as the diagrams at the end of the report. The main functions are: * PLL/VCXO * PAL/NTSC identification * SECAM identification * ASM ( Automatic System Manager ) * (R-Y)/(B-Y) demodulation * PLL/VCXO The PLL operates during the burstkey period;...
3DQDVRQLF ident stage of the Automatic System Manager (IDS signal). The H/2 switch distributes the demodulated signal to the (R-Y) and (B-Y) amplifiers and via the PAL/SECAM switch (PS) to the baseband delay line. The bypass mode of the delay line is not possible for SECAM. The V and U signals from delay line outputs are fed to the YUV selection circuit (see YUV/RGB...
3DQDVRQLF Fig 9 : Block diagram: Color decoder...
3DQDVRQLF 1.1.7 AFC - Tuning - ATS IF VCO tuned circuit The IF VCO tuned circuit is applied to pin 3 and 4 of the TDA8844. The resonance frequency is two times the IF-frequency suitable for IF standard of 38.9 MHz. The VCO frequency can be adjusted by C bus, so there is no need to readjust the external coil.
3DQDVRQLF Automatic Tuning System(ATS) The Automatic Tuning System initiates a full auto-search of the channel, covering all the bands and the system available on the TV set. At the end of the search, the microcontroller uses the teletext or VPS information (when these signals are available ) to find out the TV network name of the channel.
3DQDVRQLF 1.2 Digital control signals 1.2.1 1-3-1 local keyboard The local keyboard is not made in matrix with regular scanning from the microcontroller. Instead one input of the microcontroller is used to monitor 5 keys. Pressing one key makes the resistance to the ground vary, and therefore the level at pin 33 of microcontroller 1.2.2 1-3-2 IR remote control code The IR remote control code used is Philips RC5 code.
3DQDVRQLF As shown in Fig. 13, the bi-phase code words modulate a 36Khz carrier before being transmitted via the IR LED. The 36Khz carrier renders the transmission immune to TV line scan interference. Since the repetition period of the 36Khz carrier is 27.778µs and the duty factor is 0.25, the carrier pulse duration is 6.944µs.
3DQDVRQLF 1.2.3 I C bus The microcontroller contains an I C bus transceiver hardware interface. The I C bus is a serial communication system, it requires data line ( SDA ) and associated serial clock line (SCL) ( Philips is the patent holder of the I C bus standard).
3DQDVRQLF Data transmission SDA Bus activity - memory addressing To start communication between the bus master and the slave IC the master must initiate a start condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device address (7bits) plus a READ / WRITE bit.
3DQDVRQLF 1.3 Horizontal deflection - FBT 1.3.1 General description: CRT produces an image on the screen when a controlled electron beam is focused on the screen phosphors. To achieve this, the electrons must first be created and accelerated towards the screen using a high voltage electric field.
3DQDVRQLF 64 us Horizontal deflection current Current in the transformer primary Current via the switch ( transistor Tr and diode D ) Transistor base voltage Voltage in the Cs capacitor Collector-emitter voltage Transformer terminal voltage Fig. 19: Horizontal currents and voltages waveforms...
3DQDVRQLF Functioning and waveform explanation 220.127.116.11.1 From t to t At the initial moment t , the electron beam is aimed at the center of a line since the deflection current is zero (iy=0) and there is no horizontal deflection magnetic field. The capacitor Cs is charged and will be discharged between t and t .
3DQDVRQLF i +i i +i Fig. 21: between t and t Fig. 22: between t and t Then we can evaluate the voltages and current waveforms from t to t as presented on figure 19. There are only L and C components in the circuit, therefore we can assume that the current i has a sinus shape as shown on figure 19: cosΩt (I...
3DQDVRQLF By replacing I value to the different formula. and as L >> 1/ (C ) final results between t and t the following: cosΩ Ω = cosΩ = constant ) C L L Ω Ω − • From t to t At t , the beam is now positioned at the felt-hand side of the screen.
3DQDVRQLF 1.4.2 Drive circuit part The deflection coil drive circuit part can be represented by the following figure 27 V0(guard) V FB CURRENT SOURCE I301 TDA8356 V0(A) Deflection Coil I dri (+) V dri (-) L302 Vi(FB) I501 Idiff R302 TDA8844 L301 V dri (+)
3DQDVRQLF Waveforms obtained: Fig. 28: Vertical deflection current and voltage waveforms...
3DQDVRQLF 1.5 Video amplifier and ABS 1.5.1 Video output amplification block diagram and functional description TDA6106Q R911 R912 R913 C907 1.5k C908 CATHODE C909 100k R901 R907 R904 R902 R908 R905 R903 R909 R906 Fig.29: Video amplification diagram The video output amplification is performed by the TDA6106Q IC which is a monolithic amplifier. It can be seen as an operational amplifier with negative feedback.
3DQDVRQLF − Vo p d p A p ( ) ( ) The signal gain : G = A p K p ( ) ( ) Vi p Generally, at low frequencies, A(p) >> is valid, we can approximate this formula K p ( ) −...
3DQDVRQLF 1.5.2 ABS operation The basic application of the ABS with video output amplifiers is shown in Fig 32 below. TDA 6106Q I Black F.B. R515 100K CATHODES R511 R901 R907 R512 R902 R908 R904 19,20,21 R513 R903 R909 R905 Black current input RGB outputs R906...
3DQDVRQLF The three video amplifiers have a beam current output I black, used by the TDA8844 black current loop to control the black level on the cathodes. The outputs can be connected together because tile black current loop sequentially controls the black level far each cathode. During leakage measurement (LO) the RGB outputs are blanked implying no current flowing in CRT.
3DQDVRQLF 1.6 Power supply STR-S5707 1.6.1 Vin terminal, start-up circuit A start-up circuit is to start and stop a operation of a control IC by detecting a voltage appearing at a Vin terminal (pin 9). At start up of a power supply, when a voltage at the Vin terminal reaches to 8V (typical) by charging up C817 by the function of a start-up resistor, R804, a control circuit starts operating by the function of the start-up circuit.
3DQDVRQLF 1.6.6 Latch Circuit Latch circuit which sustains an output from the oscillator low and stops operation of the power supply when over-voltage protection (OVP) circuit and thermal shutdown (TSD) circuit are in operation. As the sustaining current of the latch circuit is 500 maximum when Vin terminal voltage is 4V, the power supply circuit sustains the off state as long as current of 500 minimum flows to Vin terminal...
3DQDVRQLF 2 VCR PART 2.1 KEY FEATURES OF VIDEO AND ITS RELATIVES 1. LA71511M (QOP 80 PIN): LUMINANCE−CHROMINANCE AND NORMAL AUDIO PROCESSING IC 1) Applicable to Multi system: PAL-GBI, MESECAM, 4.43NTSC and NAP-GBI 2) Built-in NAP circuit to convert NTSC to PAL. 3) Normal audio signal processing circuit.
3DQDVRQLF 2.2 RECORD AND PLAYBACK PROCESSING CIRCUIT 2.2.1 RECORD PROCESSING MICOM 93rd pin Video Video AGC Sync. Sep. Input Pre-amp IC 5th pin Luminance Signal Processing Chrominance Signal Processing Record Processing The video input signal selected by the AV switching IC among AUX video input and IF video input, is supplied to the 35th pin of AV 1CHIP IC.
3DQDVRQLF 2) CHRONOMINANCE SIGNAL PROCESSING (RECORD) Pre-amp 10th pin BPF1 Main C-LPF Kill Conv Det. Chrominance Signal Processing (Record) The pure chrominance signal is obtained by BPF1(fsc :4.43MHz) through filters the input signal through FBC. The gain of ACC AMP is controlled by DC voltage at 13th pin. The MAIN CONVERTER down-converts the chromiance signal with signal carrier of 4.43MHz to the signal with signal carrier of 627KHz.
3DQDVRQLF (e) As the output of the 4.3MHz BPF has ANTI-BELL batture, the signal is applied to the 4.3MHz BELL FILTER to equalize its level and group delay vs frequency. The center frequency of the BELL FILTER adjusted automatically tin the V-SYNC period based on the crystal frequency. A capacitor connected to pin 22 is to hold this frequency.
3DQDVRQLF 2.2.2 PLAYBACK PROCESSING Pre-amp luminance signal 7th pin processing Video Y/C mix chrominance signal processing OSD IC PB Enve 18th pin Playback Processing The playback ENVELOPE signal from the PRE-AMP is supplied to the 21st pin of SECAM-L IC for processing the SECAM color, and to 15th pin of A/V IC for processing the PAL color, luminance respectively.
3DQDVRQLF 2)CHROMINANCE SIGNAL PROCESSING (PB) Pre-amp AGC Amp. Phase Comp. BPF2 BPF1 7th pin Amp. Kill 2H Delay (LC89978M) Y/C Mix Chrominance Signal Processing (Playback) The down converted chrominance signal is obtained from PB ENVE signal by LPF first. And then the signal is up-converted to 4.43MHz by the MAIN CONVERTER. The redundant harmonics is filtered out by the BPF, and then the signal is applied to the CCD IC to reduce the chrominance crosstalk.
3DQDVRQLF 3) SECAM COLOR SIGNAL PROCESSING (PB) PB IN 1.1M 1.1M 1.1M ACC1 Bell Pre-BPF SECAM 2.2M Y-FM 4.4M Sync Compress Pulse Sync. Sync. 4.3M ACC2 compress. Gate PAL / NTSC REC Chroma IN SECAM Colour Signal Processing (Play Back) (a) PB signal (SECAM chrominance signal mixed with Y-FM signal) from the PRE-AMP is applied to the #21.
3DQDVRQLF 2.2.3 AUDIO SIGNAL PROCESSING (LA71511M) The circuitry of AUDIO part is similar to that of the conventional AUDIO part in case of EE and PB mode, but in REC mode, due to the internal operation of self-alignment, it shows a lot of differences. 1.
3DQDVRQLF (3) The output AUDIO signal at the 1st pin through REC AMP is recorded on HEAD after being mixed with the 70KHz AC BIAS signal. At the same time, the output AUDIO signal is supplied to the 3rd pin and then filtered by 60KHz HPF, so only the 70KHz AC BIAS signal is passed.