Sony HMD-M11 Service Manual page 87

DIGITAL BOARD IC202
Pin No. Pin Name I / O
1 INRP I
2 INRM I
3 REFI I
4 AVDD —
5 AVSS —
6 APD I
7 NU —
8 NU —
9 TEST1 I
10 LRCK1 I
11 BCK1 I
12 ADDT O
13 V35A —
14 VSS1 —
MCKI I
15
16 DPD I
17 VSS2 —
18 RES I
19 MODE I
20 SHIFT I
21 XLATCH I
22 256CK O
23 V35D —
24 VSS2 —
25 512FS O
26 BCK2 I
27 DADT I
28 LRCK2 I
29 VDD2 —
30 R1 O
31 AVDDR —
32 R2 O
33 AVSSR —
34 XVDD —
35 XOUT O
36 XIN I
37 XVSS —
38 AVSSL —
39 L2 O
40 AVDDL —
41 L1 O
42 VDD2 —
43 VDD1 —
CXD8607N (A/D, D/A CONVERTER)
R-ch analog signal (+) input terminal
R-ch analog signal (–) input terminal
Reference voltage (+3.3V) input terminal (for A/D converter section)
Power supply terminal (+5V) (for A/D converter section, analog system)
Ground terminal (for A/D converter section, analog system)
Power down detection input of the A/D converter section (for analog section)
Not used (open)
Not used (open)
Input terminal for the test (fixed at "L")
L/R clock signal (44.1 kHz) input from the CXD2650R (IC121) (for A/D converter section)
Bit clock signal (2.8224 MHz) input from the CXD2650R (IC121) (for A/D converter section)
Recording data output terminal
Power supply terminal (+3.3V) (for analog system)
Ground terminal (for A/D converter section, digital system)
Master clock (256Fs=11.2896 MHz) input of the A/D converter section
Reset signal input from the mechanism controller (IC100)
signal of power down to A/D converter (digital section)
Ground terminal (for D/A converter section, digital system)
Reset signal input from the mechanism controller (IC100)
Reset signal is used as a initialize signal to D/A converter section
Writing data input from the mechanism controller (IC100)
Serial clock signal input from the mechanism controller (IC100)
Serial latch signal input from the mechanism controller (IC100)
256Fs (11.2896 MHz) clock signal output terminal
Power supply terminal (+3.3V) (for digital system)
Ground terminal (for D/A converter section, digital system)
512Fs (22.5792 MHz) clock signal output to the CXD2650R (IC121)
Bit clock signal (2.8224 MHz) input from the CXD2650R (IC121) (for D/A converter section)
Playback data input terminal
L/R clock signal (44.1 kHz) input from the CXD2650R (IC121) (for D/A converter section)
Power supply terminal (+5V) (for D/A converter section, digital system)
R-ch PLM signal 1 output terminal
Power supply terminal (+5V) (for R-ch side D/A converter section, analog system)
R-ch PLM signal 2 output terminal
Ground terminal (for R-ch side D/A converter section, analog system)
Power supply terminal (+5V) (for X'tal system)
System clock output terminal (22 MHz)
System clock input terminal (22 MHz)
Ground terminal (for X'tal system)
Ground terminal (for L-ch side D/A converter section, analog system)
L-ch PLM signal 2 output terminal
Power supply terminal (+5V) (for L-ch side D/A converter section, analog system)
L-ch PLM signal 1 output terminal
Power supply terminal (+5V) (for L-ch side D/A converter section, digital system)
Power supply terminal (+5V) (for A/D converter section, digital system)
– 92 –
Function
Reset signal is used as a detection
"L": reset (power down)
"L": reset (initialize)
"L": power down