Figure 32. Emmc Memory Design; Table 6. Emmc Boot Pins; Emmc Circuit Design - BeagleBone Black Reference Manual

REF: BBONEBLK_SRM
6.4.2

eMMC Circuit Design

Figure 32 is the design of the eMMC circuitry. The eMMC device is connected to the
MMC1 port on the processor. MMC0 is still used for the uSD card as is currently done on
the original BeagleBone.
The device runs at 3.3V both internally and the external I/O rails. The VCCI is an
internal voltage rail to the device. The manufacturer recommends that a 1uf capacitor be
attached to this rail, but a 2.2uF was chosen to provide a little margin.
Pullup resistors are used to increase the rise time on the signals to compensate for any
capacitance on the board.
VDD_3V3B
U5A
U7
MMC1_DAT0
V7
MMC1_DAT1
R8
MMC1_DAT2
T8
MMC1_DAT3
U8
MMC1_DAT4
V8
MMC1_DAT5
R9
MMC1_DAT6
T9
MMC1_DAT7
V9
MMC1_CMD
U9
MMC1_CLK
T13
R162
GPIO2_0
AM3358_ZCZ
The pins used by the eMMC1 in the boot mode are listed below in Table 6.
For eMMC devices the ROM will only support raw mode. The ROM Code reads out raw
sectors from image or the booting file within the file system and boots from it. In raw
mode the booting image can be located at one of the four consecutive locations in the
main area: offset 0x0 / 0x20000 (128 KB) / 0x40000 (256 KB) / 0x60000 (384 KB). For
this reason, a booting image shall not exceed 128KB in size. However it is possible to
BeagleBone Black System
Reference Manual
VDD_3V3B
U13
A3
DAT0
A4
DAT1
A5
DAT2
B2
DAT3
B3
DAT4
B4
DAT5
B5
DAT6
B6
DAT7
M5
CMD
M6
CLK
K5
RST
0,1%,DNI
MEM_MNAND_2GB

Figure 32. eMMC Memory Design

Table 6. eMMC Boot Pins
Page 54 of 108
Rev A5.2
2.2uF,6.3V
DGND
C125
DGND