Toshiba 40L7363RK Service Manual page 46

127. DDR3 SDRAM B
110 129
110 129
S I G 1 7 9 0 4
S_DDRVREF S_DDRVREF
125 129
1.5V 1.5V
1 2 1 2
C1209 C1209 C1215 C1215
0.1UF/10V 0.1UF/10V 0.01UF/25V 0.01UF/25V
1 2 1 2
S I G 1 9 9 8 4
C1210 C1210 C1216 C1216
0.1UF/10V 0.1UF/10V 0.01UF/25V 0.01UF/25V
1 2 1 2
C1211 C1211 C1217 C1217
0.1UF/10V 0.1UF/10V 0.01UF/25V 0.01UF/25V
1 2 1 2
C1212 C1212 C1218 C1218
0.1UF/10V 0.1UF/10V 0.01UF/25V 0.01UF/25V
1 2 1 2
C1213 C1213 C1219 C1219
0.1UF/10V 0.1UF/10V 0.01UF/25V 0.01UF/25V
1 2 1 2
S I G 1 4 6 3 5
C1214 C1214 C1220 C1220
0.1UF/10V 0.1UF/10V 0.01UF/25V 0.01UF/25V
IC112 IC112
H5TQ2G63DFR-PBC H5TQ2G63DFR-PBC
DDR3 SDRAM DDR3 SDRAM
[V-MDSD128M16] [V-MDSD128M16]
M_B_DDR3_A0 M_B_DDR3_A0
N3
110
A0 A0
M_B_DDR3_A1 M_B_DDR3_A1
110 P7
A1 A1
M_B_DDR3_A2 M_B_DDR3_A2
P3
110
A2 A2
M_B_DDR3_A3 M_B_DDR3_A3
110 N2
A3 A3
M_B_DDR3_A4 M_B_DDR3_A4
P8
110
A4 A4
M_B_DDR3_A5 M_B_DDR3_A5
110 P2
A5 A5
M_B_DDR3_A6 M_B_DDR3_A6
R8
110
A6 A6
M_B_DDR3_A7 M_B_DDR3_A7
110 R2
A7 A7
M_B_DDR3_A8 M_B_DDR3_A8
T8
110
A8 A8
M_B_DDR3_A9 M_B_DDR3_A9
110 R3
A9 A9
M_B_DDR3_A10 M_B_DDR3_A10
L7
110
A10/AP A10/AP
M_B_DDR3_A11 M_B_DDR3_A11
110 R7
A11 A11
M_B_DDR3_A12 M_B_DDR3_A12
N7
110
A12/BC# A12/BC#
M_B_DDR3_A13 M_B_DDR3_A13
110 T3
A13 A13
M_B_DDR3_A14 M_B_DDR3_A14
T7
110
NC NC
M7
NC NC
M_B_DDR3_BA2 M_B_DDR3_BA2
M3
110
BA2 BA2
M_B_DDR3_BA1 M_B_DDR3_BA1
110 N8
BA1 BA1
M_B_DDR3_BA0 M_B_DDR3_BA0
M2
110
BA0 BA0
M_B_DDR3_MCLKZ M_B_DDR3_MCLKZ
K7
/CK /CK
M_B_DDR3_MCLK M_B_DDR3_MCLK
J7
CK CK
M_B_DDR3_CKE M_B_DDR3_CKE
110 K9
CKE CKE
L2
/CS /CS
M_B_DDR3_RASZ M_B_DDR3_RASZ
J3
110
/RAS /RAS
M_B_DDR3_CASZ M_B_DDR3_CASZ
110 K3
/CAS /CAS
M_B_DDR3_WEZ M_B_DDR3_WEZ
L3
110
/WE /WE
S_B_DDR3_DQM0 S_B_DDR3_DQM0
110 E7
DML DML
S_B_DDR3_DQM1 S_B_DDR3_DQM1
D3
110
DMU DMU
S_B_DDR3_DQS0 S_B_DDR3_DQS0
110 F3
DQSL DQSL
S_B_DDR3_DQSB0 S_B_DDR3_DQSB0
G3
110
/DQSL /DQSL
S_B_DDR3_DQS1 S_B_DDR3_DQS1
C7
110
DQSU DQSU
S_B_DDR3_DQSB1 S_B_DDR3_DQSB1
B7
110
/DQSU /DQSU
M_B_DDR3_ODT M_B_DDR3_ODT
K1
110
ODT ODT
M_B_DDR3_RESET M_B_DDR3_RESET
T2
110
/RESET /RESET
S I R1280 R1280
G
1 4
6 3
8
1 2 L8
S I G 1 4 6 4 1
ZQ ZQ
240OHM 240OHM
H1
VREFDQ VREFDQ
0.5% 0.5%
M8
VREFCA VREFCA
A1
VDDQ VDDQ
A8
VDDQ VDDQ
C1
VDDQ VDDQ
C9
VDDQ VDDQ
D2
VDDQ VDDQ
E9
VDDQ VDDQ
F1
VDDQ VDDQ
H2
VDDQ VDDQ
H9
VDDQ VDDQ
B2
VDD VDD
D9
VDD VDD
G7
VDD VDD
K2
VDD VDD
K8
VDD VDD
N1
VDD VDD
N9
VDD VDD
R1
VDD VDD
R9
VDD VDD
1.5V
HYNIX/H5TQ2G63DFR-PBC HYNIX/H5TQ2G63DFR-PBC
mx_c0603 mx_c0603
2 1
C1222 C1222 4.7UF/6.3V 4.7UF/6.3V
1 2
C1223 C1223 1UF/6.3V 1UF/6.3V
S_B_DDR3_DQ0 S_B_DDR3_DQ0
E3 110
DQL0 DQL0
S_B_DDR3_DQ1 S_B_DDR3_DQ1
F7
110
DQL1 DQL1
S_B_DDR3_DQ2 S_B_DDR3_DQ2
F2 110
DQL2 DQL2
S_B_DDR3_DQ3 S_B_DDR3_DQ3
F8
110
DQL3 DQL3
S_B_DDR3_DQ4 S_B_DDR3_DQ4
H3 110
DQL4 DQL4
S_B_DDR3_DQ5 S_B_DDR3_DQ5
H8
110
DQL5 DQL5
S_B_DDR3_DQ6 S_B_DDR3_DQ6
G2 110
DQL6 DQL6
S_B_DDR3_DQ7 S_B_DDR3_DQ7
H7
110
DQL7 DQL7
S_B_DDR3_DQ8 S_B_DDR3_DQ8
D7
110
DQU0 DQU0
S_B_DDR3_DQ9 S_B_DDR3_DQ9
C3
110
DQU1 DQU1
S_B_DDR3_DQ10 S_B_DDR3_DQ10
C8
110
DQU2 DQU2
S_B_DDR3_DQ11 S_B_DDR3_DQ11
C2
110
DQU3 DQU3
S_B_DDR3_DQ12 S_B_DDR3_DQ12
A7
110
DQU4 DQU4
S_B_DDR3_DQ13 S_B_DDR3_DQ13
A2
110
DQU5 DQU5
S_B_DDR3_DQ14 S_B_DDR3_DQ14
B8
110
DQU6 DQU6
S_B_DDR3_DQ15 S_B_DDR3_DQ15
A3
110
DQU7 DQU7
J1
NC NC
J9
NC NC
L1
NC NC
L9
NC NC
B1
VSSQ VSSQ
B9
VSSQ VSSQ
D1
VSSQ VSSQ
D8
VSSQ VSSQ
E2
VSSQ VSSQ
E8
VSSQ VSSQ
F9
VSSQ VSSQ
G1
VSSQ VSSQ
G9
VSSQ VSSQ
A9
VSS VSS S I G 1 4 6 4 2
B3
VSS VSS
E1
VSS VSS
G8
VSS VSS
J2
VSS VSS
J8
VSS VSS
M1
VSS VSS
M9
VSS VSS
P1
VSS VSS
P9
VSS VSS
T1
VSS VSS
T9
VSS VSS
1 2
C1221 C1221 1000PF/50V 1000PF/50V
1 2
C1224 C1224 1000PF/50V 1000PF/50V
MAIN BOARD MAIN BOARD MAIN BOARD
Size Size Size Project Name Project Name Project Name
EU Lv.2 EU Lv.2 EU Lv.2
Custom Custom Custom
Date: Date: Date: Tuesday, January 29, 2013 Tuesday, January 29, 2013 Tuesday, January 29, 2013
Title : Title : Title :
127. DDR3 SDRAM B 127. DDR3 SDRAM B 127. DDR3 SDRAM B
Engineer: Engineer: Engineer:
CVP DM HW CVP DM HW CVP DM HW
Rev Rev Rev
1.00 1.00 1.00
Sheet Sheet Sheet 127 127 127 of of of 76 76 76