1
K4S643232H-TC60 (MR MAIN ASSY : IC6801, IC6802)
A
• 64M SDRAM (for Silvia)
Pin Arrangement (Top view)
B
C
Block Diagram
D
CLK
68
25-27,
60-66, 24
E
A [10:0]
LCKE
LRAS
F
68
CLK
98
1
2
Bank Select
LCBR
LWE
LCAS
Timing Register
67
20
19
CKE
CS
RAS
2
3
Data Input Register
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
18
17
CAS
WE
PDP-R06XE
3
4
LWE
LDQM
2, 4, 5, 7, 8, 9, 10, 11,
13, 74, 76, 77, 79, 80,
82, 83, 85, 31, 33, 34,
36, 37, 39, 40, 42, 45,
47, 48, 50, 51, 53, 54, 56
DQ [31:0]
16, 71,
28, 59
DQM [3:0]
4