Yamaha MCX-1000 Service Manual page 68

A B
MCX-1000
SCHEMATIC DIAGRAM (MAIN: CPU Block)
1
2
3.3
5.0 5.0
0
3
5.0
3.3
0
4
5
MAIN CPU
6
7
1
RS232C DRIVER
3.3 0
3.3
0
0 3.3
0 0
0 0
0
3.3
0
8 3.3
0
9
68
C D E
IC113~120: SN74LVCHR16245AGR
16-bit Bus Transceiver
1
1DIR
47
1A1
IC110: 74LCX14MTCX
Low Voltage Hex Inverter
I0 1 14 VCC
O0 2 13 I5
I1 3 12 O5
O1 4 11 I4
3.3
I2 5 10 O4
O2 6 9 I3
GND 7 8 O3
5.0
5.0
0.1
IC109
3.3
0 1 14 5.0
0 2 13 0
3.3 0 3 12 3.3
3.3 4 11 0.1
0.1 5 10 3.3
3.3 0.1
6 9
0 7 8 1.9
IC110
5.0 1 14 3.3
0.1 0
2 13
3.3 3.2
3 12
0 4 11 3.3
3.3 5 10 0
0 6 9 0
0 7 8 3.3
Point 1 Pin 1 of IC107
VOLTAGE REGULATOR
3.3
1.8
2.7
0
0
F G
24
2DIR
48 25
1OE 2OE
36
2A1
2 13
1B1 2B1
To Seven Other Channel To Seven Other Channel
FLASH ROM
IC107: SN74AHC2GU04HDCTR
Triple Inverters
1A 1 8 VCC
3Y 2 7 1Y
2A 3 6 3A
GND 4 5 2Y
IC102: PST572CMT-R
System Reset
1 Vcc
3 Out
+
SDRAM
2 Gnd
IC103: 74LCX245MTCX
IC101: MAX3221CPWR
IC104: 74VHCT245AMTCX
RS-232C Line Driver/Receiver Low Voltage Bidirectional Transceiver
EN 1 16 FORCEOFF T/R 1
A0 2
2 15
C1+ Vcc
Auto- A1 3
V+ 3 power down 14 GND
A2 4
C1- 4 13 DOUT
A3 5
5 12
C2+ FORCEON
A4 6
C2- 6 11 DIN
A5 7
V- 7 10 INVALID A6 8
5kΩ
A7 9
8 9
RIN ROUT
GND 10
H I
BUS BUFFER
CPLD
IC105, 106: W986416DH-7
SDRAM
CLK
CLOCK
BUFFER
CKE
CS CONTROL
SIGNAL
GENERATOR
RAS
COMMAND
DECODER
CAS
COLUMN DECODER
WE
CELL ARRAY
A10 BANK #0
MODE
A0 REGISTER
SENSE AMPLIFIER
ADDRESS
A9 BUFFER
A11
BS0
BS1
DATA CONTROL
CIRCUIT
REFRESH COLUMN
COUNTER COUNTER
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
IC108: MBM29LV320BE90T
4Mbit Flash Memory
RY/BY
RY/BY
Buffer
VCC
Erase Voltage
VSS
Generator
WE
State
Control
BYTE
RESET
Command
Register
WP/ACC
Program Voltage
BUS BUFFER
Generator Chip Enable STB
Output Enable
Logic
CE
OE
Y-Decoder
STB
Timer for
Low Vcc Detector Address
Program/Erase
Latch
X-Decoder
A20 to A0
A-1
20 VCC
19 OE
18 B0
17 B1
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
16 B2
Components having special characteristics are marked s and must be replaced
15 B3 with parts having specifications equal to those originally installed.
Schematic diagram is subject to change without notice.
14 B4
13 B5
12 B6
11 B7
J K L
IC122: PQ018EZ01ZP
Regulator
VIN 1 3 DC output
IC
2 VCC
5
GND
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DMn
DQ0
DQ
BUFFER
DQ15
UDQM
LDQM
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
DQ15 to DQ0
Input/Output
Buffers
Data Latch
Y-Gating
IC121: XC9572XL-10TQ100C
Cell Matrix
CPLD
3
JTAG
JTAG Port In-System Programming Controller
1 Controller
54
Function
I/O
Block 1
18
Macrocells
I/O
1 to 18
I/O
I/O
54 Function
Block 1
18
Macrocells
1 to 18
I/O
I/O
Blocks
54
I/O Function
Block 1
18
I/O
Macrocells
1 to 18
I/O
3
I/O/GCK
54
1 Function
Block 1
I/O/GSR
18
Macrocells
2
I/O/GTS 1 to 18