Casio CZ-1 Service Manual And Spare Parts List page 83

0.
SUB RAMs
& ROM
ACCESSES
PF7
I
PFO
RO
SUB CPU
/iP07810H
l
FDO
(Normal
HIGH
Itvtl)
AS14'
AS15'
Y3 V2
Dtcodtf
SN74LS138N
VS V6
OR
gata
SN74LS32N
W1
R1
R2
CPU
intarfaca
LSI
OL11
B20
1
1
0L17
•27
MS64H173
Oata but
07
-
00
pP04464O15L
it
an
8K
byte
RAM
whilt
jiPD23C128EC
is
a
16K
byte
ROM.
Refer
to
page 17 for the functions of each
device.
In
the
same
procedures
as for
Main CPU,
lower address bus
(ASO
~
AS7)
is
generated
from
data
bus
(0S0-
0S7)
in
CPU
interface
LSI
(MB64H173) when
signal
ALE
is
HIGH. Upper
address
bus
(AS8
-
AS1S)
are provided from Sub
CPU
directly.
Chip
select signals are
generated from
signals
AS8,
ASH
and AS15.
LSI 38
FUNCTION TABLE
Chip
lalactto*
Asa AS14 AS16
WR
RO
RAM-1
LOW
HIGH
LOW
Lor H
HIGH
RAM-2 HIGH HIGH
LOW
L
or
H HIGH
ROM
LOW
HIGH
LOW
INPUT
1
OUTPUTS
EMAIL •flier
G1 03*
c
a
a
VO VI VJ VJ V4 vt va V7
>.
M
I
X
M
L
H
L
H
L
M
L
H
L
M
L
M
L
XXX
XXX
LLC
L L
M
L
N
L
L
H M
M
L L
MUM
NHL
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