Casio CZ-1 Service Manual And Spare Parts List page 87

(1 )
Pitch
Btndtr
&
Modulitord£>
SUB
CPU.
Voltage level
from
the pitch
tauter or the
modulator
is
converted into digital
data
in
the
CPU's
built-in
ADC
(Analog to
Digital
Converter)
and output from data bus
(DO
-
D7).
fhe data
is
entered into
CPU
Interface LSI.
Sending
signal
R1,
SUB CPU
sett
Latch 3 and reads data periodically.
(2)
MAIN CPU
C^SUB
CPU.
Via Latch
1
and Decoder
1,
MAIN CPU
drops clock pulse
'0*
to
LOW
level.
By clock pulse
'0', F/F
1 is
preset to
rise
signal
SYC.
MAIN CPU
puts data
on
data
bus
DO
~
D7, and
at
the
same time, clock pulse
'0'
rises
to
HIGH
level.
At
the
rising
edge of clock pulse '0', data
from
MAIN CPU
is
set in
Latch
2.
MAIN CPU
interrupts
SUB CPU
from terminal
PB2, and simultaneously generates
signal
CONT
from terminal PB3.
Generating signal
R2 from Decoder
3,
SUB CPU
reads the data
from Latch 2
via
data
bus
DS0-DS7.
SUB CPU
sends signal
ACK
to
MAIN CPU
via
Decoder 3 and F/F
2.
Upon
receipt
of
signal
ACK,
MAIN CPU
confirms
that
SUB CPU
has received the data
and
generates signal
$16
in
Decoder
2.
When
all
the data have sent to
SUB CPU
by
repeating
the above
procedures©-®,
MAIN CPU
drops
signal
CONT
to
LOW.
Confirming
that
both
CONT
and
SYC
are
LOW,
SUB CPU
determines
that
all
the data
have been
received.
Latch 2 1st data
X
2nd
data
X
3rd
data (
X
Last data
1
1 1 1
I
)
MAIN CPU
PB2
n
n
n
)
n
X896 J~~L
n
1
-1
CONT
-26-