System Control Block Diagram - Aiwa XD-AX10 Service Manual

XD-AX10
Q Q
3 7 6 3 1 5 1 5 0

3-4. SYSTEM CONTROL BLOCK DIAGRAM

MB-108 BOARD (3/4)
(SEE PAGE 4-9, 10)
HA 0 – 21
HD 0 – 15
XRD
XWRH
SIGNAL PROCESSOR
(SEE PAGE 3-5)
XARPIT
XARPCS
XWAIT
XRST
XRST
XSDPIT
XSDPCS
RF/SERVO
XDRVMUTE
(SEE PAGE 3-4)
XLDON
CKSW1
OCSW1
T E
L 1 3 9 4 2 2 9 6 5 1 3
XAVDIT
DREQ0
DACK0
DREQ1
DACK1
XAVDCS2
XAVDCS3
XFRRST
SIGNAL PROCESSOR
(SEE PAGE 3-5)
33MARP
27MAVD
w w w
512FSAVD
05
IC106 IC107
or
32M FLASH OTP
HA 0 – 21
HD 0 – 15
1 – 5 102 – 109 111 – 118 120 85 – 100
HA 0 – 21
70 XRD
71 XWRH
17 INT1
62 CS4X
67 XWAIT
35 XRST
18 INT2
63 CS5X
48 XDRVMUTE
82 WIDE
56 CKSW1
57 OCSW1
IC101
EEPROM
WP 7 7 WP
SCL 6 39 SCL
SDA 5 38 SDA
16 INTO
46 DREQ0
47 DACK0
49 DREQ1
50 DACK1
60 CS2X
61 CS3X
81
4
IC103 qg
3.3Vp-p
30nsec
x a o
y
. i
3-7
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58 59 72 84
HD 0 – 15
X1 (OUT)
53
X101
16.5MHz
X2 (IN) 54
XARPRST 36
EXT/DSEL 42
RGBSEL
37
EUROVY 41
IC104
SYSTEM
CONTROL
Q Q
SI0 25
3 7 6
SO0 26
SCO 27
XIFCS 51
INT4 20
XFRRST 76
MA MUTE 83
SO1 29
SC1 30
XDACS 79
2
IC103 8
IC103
PLL
3.3Vp-p
38nsec
XTI
7
14 FSEL
X102
27MHz
XTO 8
15 33-1OUT 512-2OUT 9
3 27-1OUT 512-1OUT 10
1
IC103 3
u 1 6 3
3.3Vp-p
1.17msec
.
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2 4
8 9 9
5
IC104 tf
3.3Vp-p
60nsec
3 1 5 1 5 0 8 9 2
MA MUTE
SO1
SC1
XDACS
AUDIO
XRST
(SEE PAGE 3-11)
3
IC103 9 q;
3.3Vp-p
42nsec
512FS2CH
m
c o
3-8
2
8 9 9
CN601
(2/3)
2 WIDE
10 EXT/DSEL
VIDEO
14 RGBSEL
(SEE PAGE 3-9)
12 EUROVY
CN101
4 SI0
4 9 8 2 9 9
1 SO0
INTERFACE
3 SC0
CONTROL
6 XIFCS
(SEE PAGE 3-13)
5 XIFBUSY
8 XFRRST