Pioneer XV-DV232 Service Manual page 99

5
No. Pin Name I/O
25 SCL I I2C serial control clock input output
26 LRCLK I Serial audio data left / right clock (sampling rate clock)
27 SCLK I Serial audio data clock (shift clock)
Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four discrete (stereo) data
28 SDIN4 I
formats and is capable of inputting data at 64 Fs.
Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four discrete (stereo) data
29 SDIN3 I
formats and is capable of inputting data at 64 Fs.
Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four discrete (stereo) data
30 SDIN2 I
formats and is capable of inputting data at 64 Fs.
Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four discrete (stereo) data
31 SDIN1 I
formats and is capable of inputting data at 64 Fs.
32 PSVC O Power supply volume control PWM output
−
33 VR_DIG Voltage reference for digital core supply 1.8 V.
−
34 DVSS Digital ground
−
35 DVSS Digital ground
−
36 DVDD 3.3-V digital power supply
37 BKND_ERR I Active low. A backend error sequence is generated by applying logic low to this terminal.
−
38 DVSS Digital ground
39 VALID O Output indicating validity of PWM outputs active high
40 PWM_M_1 O PWM 1 output (differential - )
41 PWM_P_1 O PWM 1 output (differential +)
42 PWM_M_2 O PWM 2 output (differential - )
43 PWM_P_2 O PWM 2 output (differential +)
44 PWM_M_3 O PWM 3 output (differential - )
45 PWM_P_3 O PWM 3 output (differential +)
46 PWM_M_4 O PWM 4 output (differential - )
47 PWM_P_4 O PWM 4 output (differential +)
−
48 VR_PWM Voltage reference for digital PWM core supply 1.8 V.
49 PWM_M_7 O PWM 7 (Line out L) output (differential - )
50 PWM_P_7 O PWM 7 (Line out L) output (differential +)
51 PWM_M_8 O PWM 8 (Line out R) output (differential - )
52 PWM_P_8 O PWM 8 (Line out R) output (differential +)
−
53 DVSS_PWM Digital ground for PWM
−
54 DVDD_PWM 3.3-V digital power supply for PWM
55 PWM_M_5 O PWM 5 output (differential - )
56 PWM_P_5 O PWM 5 output (differential +)
57 PWM_M_6 O PWM 6 output (differential - )
58 PWM_P_6 O PWM 6 output (differential +)
59 PWM_HPML O PWM left channel headphone (differential - )
60 PWM_HPPL O PWM left channel headphone (differential +)
61 PWM_HPMR O PWM right channel headphone (differential - )
62 PWM_HPPR O PWM right channel headphone (differential +)
MCLK is a 3.3-V clock master clock input. The input frequency of this clock can range from 4 MHz to 50
63 MCLK I
MHz.
−
64 RESERVED Connect to digital ground
5
6
Pin Function
XV-DV232
6
7
7
8
A
B
C
D
E
F
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