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HYUNDAI MicroElectonics
MNEMONIC
NO.
79
EOR #imm
80
EOR dp
81
EOR dp + X
82
EOR !abs
83
EOR !abs + Y
84
EOR [ dp + X ]
85
EOR [ dp ] + Y
86
EOR { X }
87
EOR1 M.bit
88
EOR1B M.bit
89
INC A
90
INC dp
91
INC dp + X
92
INC !abs
93
INC X
94
INC Y
95
INCW
dp
96
JMP !abs
97
JMP [!abs]
98
JMP [dp]
99
LDA #imm
100
LDA dp
101
LDA dp + X
102
LDA !abs
103
LDA !abs + Y
104
LDA [ dp + X ]
105
LDA [ dp ] + Y
106
LDA { X }
107
LDA { X }+
108
LDC M.bit
109
LDCB M.bit
110
LDM dp,#imm
111
LDX #imm
112
LDX dp
113
LDX dp + Y
114
LDX !abs
115
LDY #imm
116
LDY dp
117
LDY dp + X
118
LDY !abs
119
LDYA dp
120
LSR A
121
LSR dp
122
LSR dp + X
123
LSR !abs
68
OP
BYTE
CYCLE
CODE
NO
NO
A4
2
2
Exclusive OR
A5
2
3
A
A6
2
4
A7
3
4
B5
3
5
96
2
6
97
2
6
94
1
3
AB
3
5
Bit exclusive-OR C-flag
AB
3
5
Bit exclusive-OR C-flag and NOT : C
88
1
2
Increment
89
2
4
M
99
2
5
98
3
5
8F
1
2
9E
1
2
9D
2
6
Increment memory pair : ( dp+1) ( dp)
1B
3
3
Unconditional jump
1F
3
5
PC
3F
2
4
C4
2
2
Load accumulator
C5
2
3
A
C6
2
4
C7
3
4
D5
3
5
D6
2
6
D7
2
6
D4
1
3
DB
1
4
X- register auto-increment : A
CB
3
4
Load C-flag
CB
3
4
Load C-flag with NOT
E4
3
5
Load memory with immediate data : ( M )
1E
2
2
Load X-register
CC
2
3
X
CD
2
4
DC
3
4
3E
2
2
Load Y-register
C9
2
3
Y
D9
2
4
D8
3
4
7D
2
5
Load YA : YA
48
1
2
Logical shift right
49
2
4
59
2
5
58
3
5
OPERATION
( A ) ⊕ ( M )
: C
( M )
1
jump address
( M )
: C
( M .bit )
: C
~( M .bit )
( M )
( M )
( dp +1 ) ( dp )
7 6 5 4 3 2 1 0
"0"
( C ) ⊕ ( M .bit )
( C ) ⊕ ~( M .bit )
( dp+1) ( dp )
1
( M ) ,
X
X
1
imm
C
FLAG
NVGBHIZC
N-----Z-
-------C
-------C
N-----ZC
N-----Z-
N-----Z-
--------
N-----Z-
-------C
-------C
--------
N-----Z-
N-----Z-
N-----Z-
N-----ZC
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