Toshiba 27WLT56B Service Manual page 21

• Up to 2.38 Gbps throughput
• Up to 297.5 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
12.14.3. Pin Description
DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter
Pin Name I/O No.
I 28
TxIN
O 4
TxOUT+
O 4
TxOUT-
I 1
TxCLKIN
I 1
R_FB
O 1
TxCLK OUT+
O 1
TxCLK OUT-
I 1
PWR DOWN
I 3
Vcc
I 4
GND
I 1
PLL Vcc
I 2
PLL GND
I 1
LVDS Vcc
I 3
LVDS GND
Pin Name I/O
I
TxIN
O
TxOUT+
O
TxOUT-
I
TxCLKIN
I
R_FB
O
TxCLK OUT+
O
TxCLK OUT-
I
PWR DOWN
I
Vcc
I
GND
I
PLL Vcc
I
PLL GND
I
LVDS Vcc
I
LVDS GND
NC
27" TFT TV Service Manual
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
No. Description
28 TTL level input.
4 Positive LVDS differentiaI data output.
4
Negative LVDS differential data output.
1 TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
1
Programmable strobe select. HIGH = rising edge, LOW = falling edge.
1 Positive LVDS differential clock output.
1
Negative LVDS differential clock output.
1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low
current at power down.
3 Power supply pins for TTL inputs.
5 Ground pins for TTL inputs.
1
Power supply pin for PLL.
2 Ground pins for PLL.
2 Power supply pin for LVDS outputs.
4
Ground pins for LVDS outputs.
6
Pins not connected.
18
05/09/2005