NEC N8 Service Manual page 127

Table of Contents

Advertisement

100-Ball FSBGA
Signal Name
A11
MICIN
A10
MICOUT
A12
AUXIN
B12
AUXOUT
B10
VXVCM
E11
AOUTAP
E10
AOUTAN
C12
AOUTBP
D11
AOUTBN
B11
VREG
C11
REFC
A9
DAIRN
C9
DAIDI
A8
DAIDO
B9
DAICK
G11
TxIP
G12
TxIN
H11
TxQP
H12
TxQN
H10
TxP
F12
AFC
K11
RXIP
K12
RXIN
L12
RXQP
L11
RXQN
K10
RAREF1
J12
RAREF2
L6
MC
B1, C1, C2, C3,
DB[15:0]
D1, D2, D3, E1,
E2, E3, F2, G1,
G2, H1, H3, H2
J2, K1, K2, L1,
AB[8:0]
M1, M2, M3,
K3, L3
J1
RWN
J3
IO
M4
DINTR
L4
CINTR
C10
RESETN
PIN INFORMATION
Type*
Description
I, A
Voice band microphone input.
O, A
Voice band microphone feedback.
I, A
Voice band auxiliary input.
O, A
Voice band auxiliary feedback.
I, A
Voice band external bypass capacitor, reference.
O, A
Voice band positive output number 1.
O, A
Voice band negative output number 1.
O, A
Voice band positive output number 2.
O, A
Voice band negative output number 2.
O, A
Voice band regulated voltage for electrect cond.
microphone.
O, A
Voice band external capacitor for internal voltage
regulator.
I, D, PD
Voice band digital audio interface reset not. Active-low.
I, D, PD
Voice band digital audio interface data in.
O, D
Voice band digital audio interface data out. Reset state
is low.
O, D
Voice band digital audio interface clock. Reset state is
high.
O, A
Baseband transmit I component positive output.
O, A
Baseband transmit I component negative output.
O, A
Baseband transmit Q component positive output.
O, A
Baseband transmit Q component negative output.
O, A
Baseband transmit power control DAC output.
O, A
Automatic frequency control DAC output.
I, A
Baseband receive I component positive input.
I, A
Baseband receive I component negative input.
I, A
Baseband receive Q component positive input.
I, A
Baseband receive Q component negative input.
O, A
RX baseband analog reference for ADC.
O, A
RX baseband analog reference for ADC.
I, A
Small-signal master clock single-ended input.
I/O, D
Data bus 15-0
I, D
Address bus 8-0.
I, D
Read/write not (low = write, high = read).
I, D
Chip select to enable data bus I/O.
O, D
Interrupt output to DSP. Active-high, reset state is low.
O, D
Interrupt output to microcontroller. Active-high, reset
state is low.
I, D
Reset not. Active-low.
NEC Confidential & Proprietary

Advertisement

Table of Contents
loading

Table of Contents