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Mesa 7i92 Manual

Ethernet anything i/o
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7I92 ETHERNET
ANYTHING I/O
MANUAL
Version 1.7

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Summary of Contents for Mesa 7i92

  • Page 1 7I92 ETHERNET ANYTHING I/O MANUAL Version 1.7...
  • Page 2 This page intentionally not blank...

  • Page 3: Table Of Contents

    7I92 I/O CONNECTOR PIN-OUT ........5...
  • Page 4 Table of Contents OPERATION ............8 MESAFLASH .
  • Page 5 INFO AREA ACCESS ........21 7I92 SUPPORTED MEMORY SPACES ......22 SPACE0: HOSTMOT2 REGISTERS .

  • Page 6: General

    The 7I92 provides 34 I/O bits (17 per connector) All I/O bits are 5V tolerant and have pullup resistors. A power source option allows the 7I92 to supply 5V power to breakout boards if desired. This 5V power is protected by a PTC.

  • Page 7: Hardware Configuration

    CONNECTOR 5V POWER The 7I92 has the option to supply 5V power from the to the breakout board. This option is used by all Mesa breakout boards to simplify wiring. The option uses 4 parallel cable signals that are normally used as grounds for supplying 5V to the remote breakout board (DB25 pins 22,23,24 and 25).

  • Page 8: Preconfig Pull-Up Enable

    Jumpers W5 and W6. IP ADDRESS DOWN DOWN FIXED 192.168.1.121 (DEFAULT) DOWN FIXED FROM EEPROM DOWN BOOTP INVALID Note: that the initial EEPROM IP address is set to 10.10.10.10 at Mesa, but can be changed to any address with the mesaflash utility. 7I92...

  • Page 9: Connectors

    CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS 7I92...

  • Page 10: 7I92 I/O Connector Pin-Out

    CONNECTORS I/O CONNECTORS The 7I92 has 2 I/O connectors, P1 and P2 please see the 7I92IO.PIN file on the 7I92 distribution disk. Depending on 7I92 model P2 may be a DB25 female, DB25 male or 26 pin header. 7I92 IO P2 connector pinouts are as follows:...
  • Page 11 Note: 26 pin header P1 will match standard parallel port pin-out if terminated with flat cable 26 pin receptacle/DB25F cable with pin1s connected (and header pin 26 left open) A cable kit is available from MESA for the second port. 7I92...

  • Page 12: Power Connector Pinout

    P4 is a JTAG programming connector. This is normally used only for debugging or if both EEPROM configurations have been corrupted. In case of corrupted EEPROM contents the EEPROM can be re-programmed using Xilinx’s Impact tool. P4 JTAG CONNECTOR PINOUT FUNCTION +3.3V 7I92...

  • Page 13: Operation

    Ethernet EEPROM locations 0x20 and 0X22. BootP allows the 7I92 address to be set by a DHCP/ BootP server. If BootP is chosen, the 7I92 will retry BootP requests at a ~1 Hz rate if the BootP server does not respond.

  • Page 14: Configuration

    16M bit chip that has space for two configuration files. Since all Ethernet logic on the 7I92 is in the FPGA, a problem with configuration means that Ethernet access will not be possible. For this reason there is a backup method to recover from FPGA boot failures, fallback.

  • Page 15: Eeprom Layout

    OPERATION EEPROM LAYOUT The EEPROM used on the 7I92 for configuration storage is the M25P16. The M25P16 is a 16 M bit (2 M byte) EEPROM with 32 64K byte sectors. Configuration files are stored on sector boundaries to allow individual configuration file erasing and updating.
  • Page 16 USER CONFIGURATION BLOCK 2 0x130000 USER CONFIGURATION BLOCK 3 0x140000 USER CONFIGURATION BLOCK 4 0x150000 USER CONFIGURATION BLOCK 5 0x160000 UNUSED/FREE 0x170000 UNUSED/FREE 0x180000 UNUSED/FREE 0x190000 UNUSED/FREE 0x1A0000 UNUSED/FREE 0x1B0000 UNUSED/FREE 0x1C0000 UNUSED/FREE 0x1D0000 UNUSED/FREE 0x1E0000 UNUSED/FREE 0x1F0000 UNUSED/FREE 7I92...

  • Page 17: Bitfile Format

    -g CRC:enable bitgen options must be set. WARNING: Never write a bitfile that is not designed for a 7I92 into the 7I92s EEPROM as this will likely "brick" the 7I92 card and require the card to be returned to Mesa for repair.

  • Page 18: Free Eeprom Space

    (faster) JTAG FPGA load followed by Ethernet EEPROM update. CLOCK SIGNALS The 7I92 has a single 50 MHz clock signal from an on card crystal oscillator. The clock a can be multiplied and divided by the FPGAs clock generator block to generate a wide range of internal clock signals.

  • Page 19: Leds

    OPERATION LEDS The 7I92 has 4 FPGA driven user LEDs (User 0 through User 3 = Green), and 2 FPGA driven status LEDs (red) and a power LED. The user LEDs can be used for any purpose, and can be helpful as a simple debugging feature. A low output signal from the FPGA lights the LED.

  • Page 20: Interface Cables

    OPERATION INTERFACE CABLES Mesa daughtercards use a male to male DB25 cable to interface to the 7I92. For noise immunity and signal fidelity it is suggested that only IEEE-1284 rated cables be used. IEEE-1284 rated cables have a twisted pair shield wire for each signal wire and an overall shield terminated in the metal connector shell.

  • Page 21: Supplied Configurations

    (four used locally on the 7I77s and two fed through for additional remotes), a watchdog timer and GPIO. 7I77_7I76D 7I77_7I76D is a configuration intended to work with a7I77 six axis analog servo daughtercard on P2 a 7I76 daughtercard on P1. 7I92...

  • Page 22: 7I77_7I74D

    Each of the configurations has an associated file with file name extension .pin that describes the FPGA functions included in the configuration and the I/O pinout. These are plain text files that can be printed or viewed with any text editor. 7I92...

  • Page 23: Reference Information

    LBP16 read commands are followed by the 16 bit address (if the A bit is set). LBP16 Write commands are followed by the address (if bit A is set) and the data to be written. LBP16 Addresses are always byte addresses. LBP data and addresses are little endian so must be sent LSB first. 7I92...

  • Page 24: Info Area

    Is type: 01 = Register, 02 = Memory, 0E = EEPROM, 0F = Flash Is access types (bit 0 = 8 bit, bit 1 = 16 bit etc)so for example 0x06 means 16 bit and 32 bit operations allowed 7I92...

  • Page 25: Info Area Memranges Format

    REFERENCE INFORMATION LBP16 INFO AREA MEMRANGES FORMAT Is erase block size Is Page size Ps address range Ranges are 2^E, 2^P, 2^S. All sizes and ranges are in bytes. E and P are 0 for non-flash memory 7I92...

  • Page 26: Info Area Access

    Ispace 3 read with address NN6DLLHH FPGA flash space Ispace 3 read NN2D Ispace 6 read with address NN79LLHH LBP16 R/W space Ispace 6 read NN39 Ispace 7 read with address NN7DLLHH LBP16 R/O space Ispace 7 read NN3D 7I92...

  • Page 27: 7I92 Supported Memory Spaces

    LBP16 7I92 SUPPORTED MEMORY SPACES The 7I92 firmware supports 6 address spaces. These will be described individually with example hexadecimal commands. The hex command examples below are written in LSB first order for convenience. In the hex command examples, the NN is the count/increment field of the LBP16 command and the LLHH is the low and high bytes of the address.
  • Page 28 ; 32 bit data for GPIO port 0 at 0x1004 CCCCCCCC ; 32 bit data for GPIO port 0 at 0x1008 DDDDDDDD ; 32 bit data for GPIO port 0 at 0x100C Note like all LBP16 data, write data is LS byte first 7I92...

  • Page 29: Space1: Ethernet Chip Access

    IP address. The Ethernet EEPROM space is accessed as 16 bit data. The first 0x20 bytes are read only and the remaining 0x60 bytes are read/write. Space 2 read with address NN49LLHH Space 2 write with address NNC9LLHH Space 2 read NN09 Space 2 write NN89 7I92...

  • Page 30: Ethernet Eeprom Layout

    ETHERNET EEPROM LAYOUT ADDRESS DATA 0000 Reserved RO 0002 MAC address LS Word RO 0004 MAC address Mid Word RO 0006 MAC address MS Word RO 0008 Reserved RO 000A Reserved RO 000C Reserved RO 000E Unused RO 7I92...
  • Page 31 EEPROM Netmask LS word RW (V16 and > firmware) 0026 EEPROM Netmask MS word RW (V16 and > firmware) 0028 DEBUG LED Mode (LS bit determines HostMot2 (0) or debug(1)) RW 002A Reserved RW 002C Reserved RW 002E Reserved RW 0030..007E Unused RW 7I92...

  • Page 32: Space3: Fpga Flash Eeprom Chip Access

    The page write is started by writing the flash address, reading the flash address, reading flash data, reading flash ID or issuing a erase sector command. For host synchronization, a read operation should follow every sector erase or page write. 7I92...
  • Page 33 Issue write flash data command with count 12345678 Doubleword 0 ABCD8888 Doubleword 1 ....FFFFFFFF Doubleword 63 (= 256 bytes) 014E0000 Read new address to commit write and so some data is returned for host synchronization (so host waits for write to complete) 7I92...
  • Page 34 Write EEPROMWEna with 0x5A03 01CE000000000100 Write flash address with 0x 00010000 01CE0C0000000000 Write sector erase command (with dummy 32 bit data = 0) 014E0000 Read flash address for host synchronization (this will echo the address _after_ the sector is erased) 7I92...

  • Page 35: Space4: Lbp Timer/Util Registers

    0010..001E Scratch registers for any use The uSTimeStamp register reads the free running hardware microsecond timer. It is useful for timing internal 7I92 operations. Writes to the uSTimeStamp register are a no- op. The WaituS register delays processing for the specified number of microseconds when written, (0 to 65535 uS) reads return the last wait time written.

  • Page 36: Space6: Lbp Status/Control Registers

    Space 6 write with address NND9LLHHDDDD Space 6 read NN19 Space 6 write NN99DDDD MEMORY SPACE 6 LAYOUT: ADDRESS DATA 0000 ErrorReg 0002 LBPParseErrors 0004 LBPMemErrors 0006 LBPWriteErrors 0008 RXPktCount 000A RXUDPCount 000C RXBadCount 000E TXPktCount 00010 TXUDPCount 00012 TXBadCount 7I92...

  • Page 37: Error Register Format

    001C LBPReset Setting this to a non-zero value will do a full reset of the LBP16 firmware. The 7I92 will read its IP address jumpers and re-assign its IP address. The 7I92 will be unresponsive for as much as ½ of a second after this command.

  • Page 38: Space7: Lbp Read Only Information

    0006 CardNameChar-6,7 0008 CardNameChar-8,9 000A CardNameChar-10,11 000C CardNameChar-12.13 000E CardNameChar-14,15 0010 LBPVersion 0012 FirmwareVersion 0014 Option Jumpers 0016 Reserved 0018 RecvStartTS 1 uSec timestamps 001A RecvDoneTS For performance monitoring 001C SendStartTS Send timestamps are 001E SendDoneTS from previous packet 7I92...

  • Page 39: Elbpcom

    ELBPCOM ELBPCOM is a very simple demo program in Python (2.x) to allow simple checking of LBP16 host communication to the 7I92. ELBPCOM accepts hexadecimal LBP16 commands and data and returns hexadecimal results. Note that the timeout value will need to be increased to about 2 seconds to try flash sector erase commands.

  • Page 40: Specifications

    INPUT VOLTAGE 5V TOL MODE -0.3V INPUT VOLTAGE 3.3V TOL MODE -0.3V OUTPUT VOLTAGE 24 MA SINK ---- 0.6V FPGA outputs set for 24 MA drive OUTPUT VOLTAGE 24 MA SOURCE 2.4V ---- FPGA outputs set for 24 MA drive 7I92...

  • Page 41: Card Drawing

    REFERENCE INFORMATION CARD DRAWING 7I92...

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