Harman Kardon AVR 1650 Service Manual page 96

AVR 1650
ESMT
SDRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
-
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
PIN CONFIGURATION (TOP VIEW)
V 1
DD
DQ0 2
DQ1 3
V 4
SSQ
DQ2 5
DQ3 6
V 7
DDQ
DQ4 8
DQ5 9
V 10
SSQ
DQ6 11
DQ7 12
V 13
DDQ
LDQM 14
15
WE
CAS 16
RAS 17
CS 18
BA 19
A10/AP 20
A0 21
A1 22
A2 23
A3 24
V 25
DD
Elite Semiconductor Memory Technology Inc.
V
50
SS
49 DQ15
DQ14
48
V
47
SSQ
DQ13
46
DQ12
45
V
44
DDQ
DQ11
43
42 DQ10
41 V
SSQ
40 DQ9
39 DQ8
38 V
DDQ
37 N.C/RFU
36 UDQM
CLK
35
CKE
34
N.C
33
A9
32
A8
31
A7
30
29 A6
28 A5
27 A4 50PIN TSOP(II)
(400mil x 825mil)
26 V
SS
(0.8 mm PIN PITCH)
512K x 16Bit x 2Banks
Synchronous DRAM
GENERAL DESCRIPTION
The M12L16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO. MAX Freq.
M12L16161A-5TG
200MHz
M12L16161A-7TG
143MHz
M12L16161A-7BG
143MHz
1 2 3
A VSS DQ15
B
DQ14 VSSQ
DQ13 VDDQ
C
D DQ12 DQ11
E
DQ10 VSSQ
F
DQ9 VDDQ
G DQ8 NC
H NC
NC
NC UDQM
J
NC CLK
K
CKE
NC
L
A9
M A11
A8 A7
N
P A6 A5
VSS A4
R
96
harman/kardon
M12L16161A
PACKAGE COMMENTS
TSOP(II) Pb-free
TSOP(II) Pb-free
VFBGA Pb-free
4 5 6 7
DQ0
VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
VDDQ DQ5
VSSQ
DQ6
NC DQ7
NC
NC
LDQM WE
RAS CAS
NC
CS
NC NC
A0 A10
A1
A2
60 Ball VFBGA
A3 VDD
(6.4x10.1mm)
(0.65mm ball pitch)
Publication Date : May. 2005
Revision : 2.4 2/30