Components - N1400, N1430 - Sony Ericsson C702 Troubleshooting Manual

N1400 Module Bluetooth + FM Radio STLC2592 1200-6182
BLOCK DIAGRAM AND ELECTRICAL SCHEMATIC
F M _ V A F M _ V D
RECEIVER DEMOD
BT_RFP
F
I
L
RF PLL CONTROL
T Fractional N
AND
E REGISTER
R
BT_RFN
TRANSMITTER MOD
BASEBAND
CORE EBC
AUTOCALIBRATION
PLL
BT _REF_CLK_IN
Headphone
Cable
I
ADC
FM_FMIP
LNA VGA
Q
ADC
0 / 90
AGC
FM_RCLK TUNE AFC
NC BT_REG_ FM_GND BT _RSRV
FM_RFGND
[ 5:0] CTRL [7:0] [4:0]
Pinout Bottom View
1 2 3 4 5 6
FM_GND FM_VA FM_GPIO3 FM_GPIO2
A
BT_RSRV_CL FM_VD FM_GND FM_LOUT FM_GND
B
BT_RSRV_DSM BT_RSRV_N BT_RSRV_CL FM_GND FM_ROUT FM_GND
C
BT_VSSANA BT_VSSANA BT_HVA NC FM_GND FM_VIO
D
BT_HVA BT_VDD_CLD
BT_HVA BT_VSSANA BT_HVA
E
BT_VSSANA BT_VSSANA BT_VSSANA BT_VSSANA BT_REF_CLK_IN
F
BT_VSSANA BT_TEST2 BT_VSSANA BT_VSSANA BT_AF_PRG
G
BT_VSSRF BT_TEST1 BT_VSSANA BT_VSSANA BT_VSSDIG
H
BT_UART_RTS
BT_RFN BT_VSSRF BT_GPIO_16 BT_REG_CTRL
BT_SPI_CSN
J
BT_UART_CTS
BT_RFP BT_VSSRF BT_GPIO_11 BT_GPIO_10 BT_PCM_A
BT_SPI_CLK
K
BT_VSSRF BT_HVA BT_GPIO_8 NC NC NC
L
BT_RSRV_RF BT_GPIO_9 BT_PCM_CLK BT_PCM_B BT_VIO_A
M
BT_VIO_C BT_PCM_SYNC BT_VIO_D BT_CONFIG_3
N
APPENDIX
B T _ H V : 5 [ ] 0 B T _ I V O : 4 [ ] 0
BT_GPIO
[5:0]
ARM7TDMI
CPU Wrapper
BT_LP_CLK
JTAG
RAM BT_HOST_WAKEUP/
BT_SPI _INT
ROM
BT _WAKEUP
UART / SPI
BT _RESETN
TIMER
BT_UART/
BT _SPI [3:0]
AMBA
INTERRUPT
PERIOH .
BUS
BT_PCM
[3:0]
PCM
BT_CONFIG
WLAN [2:0]
I2C
BT_CLK_REQ_IN
[ 1:0]
BT_CLK_REQ_OUT
[1: 0]
DAC
DSP
FM_LOUT
FILTER
DEMOD
MPX
FM_ROUT
AUDIO
DAC
FM_GPIO
LOW-IF GPIO
[2:0]
FM_VIO
RDS
FM_RSTB
FM_SDIO
FM_SCLK
RSSI
FM_SENB
BT_TEST BT_VSS
BT_VDD_CLD BT _AF_PRG
[1:0] [ 20: 0]
7 8 9
FM_GPIO1
FM_GND FM_FMIP
FM_GND FM_RFGND FM_RSTB
FM_RCLK FM_SDIO FM_SENB
BT_CLK_ BT_HOST_WAKEUP
FM_SCLK
REQ_IN1 BT_SPI_INT
NC NC BT_CLK_REQ_IN2
BT_UART_TXD
BT_VIO_E BT_GPIO_0
BT_SPI_DO
BT_UART_RXD
BT_VSSDIG BT_VSSDIG
BT_SPI_DI
BT_CLK_ BT_CLK_
BT_VIO_B
REQ_OUT1 REQ_OUT2
BT_RESETN BT_VSSDIG BT_LP_CLK
BT_CONFIG_1 BT_VSSDIG BT_WAKEUP
BT_CONFIG_2 BT_RSRV_D
BT_HVD

Components - N1400, N1430

N1430 IC A-GPS Hammerhead 2 1200-0700
Multiplexed Core System
Serial Interface Supply Integration
VDD_CORE
OMS2
OMS1
OMS0
SYNC
CNTIN VDD_CORE
CLK nRESET
Hammerhead II
(SG-UFWLB-49 )
VDD_PLL VDD_RFREG_IN
VDD_LP_PLLREG_IN VDD_RF
VDD_LPREG_OUT
VDD_LP
VDD_IO
JTAG Interface Decouple VCO Mixer EXT_LNA
Pin Pin Pad Pad O/P
No. Name Type Usage State
Pad Functional Description
A1 HIF3 I/O Host Interface
I - - -
UART_RXD / OMS[2:0]=[1,1,1]: UART Interface: Data Input
(I) - - -
UART_RXD / OMS[2:0]=[1,1,0]: UART Interface: Data Input (Ignored)
I - - -
2
I C_GROUP1 / OMS[2:0]=[1,0,1]: Selection of I 2 C group address
I - - -
SPI_nSCS OMS[2:0]=[1,0,0]: SPI chip select
A2 HIF4 I/O Host Interface
UART_nRTS / O - 0 0 OMS[2:0]=[1,1,1]: UART Interface: hardware flow control
Z - Z Z
UART_nRTS / OMS[2:0]=[1,1,0]: UART Interface: hardware flow control
I - - -
I 2 C_A0 / (Tristated)
I - - -
SPI_SI OMS[2:0]=[1,0,1]: Selection of I 2 C group address bit 0
OMS[2:0]=[1,0,0]: SPI serial data input
A3 CNTIN I I - - - Digital high accuracy frequency reference
A4 CLK I/AI I - - - Clock signal input. Selectable as digital or analog input
A5 VDD_PLL PI/ - - - - Digital PLL supply Decoupling
PO
A6 VDD_LP_PLLREG_I PI - - - - PLL voltage and Low Power core regulator input
N
A7 VDD_IO PI - - - - Digital I/O supply
B1 VSS_DIG GND - - - -
B2 HIF2 I/O Host Interface
O - 0 0
UART_TXD / OMS[2:0]=[1,1,1]: UART Interface: Data Output
Z - Z Z
UART_TXD / OMS[2:0]=[1,1,0]: UART Interface: Data Output (Tristated)
I - - -
2
I C_GROUP0 / OMS[2:0]=[1,0,1]: Selection of I 2 C group address
I - - -
SPI_SCK OMS[2:0]=[1,0,0]: SPI clock
B3 HIF5 I/O - - - - Host Interface
UART_nCTS / I - - - OMS[2:0]=[1,1,1]: UART Interface: hardware flow control
(I) - - -
UART_nCTS / OMS[2:0]=[1,1,0]: UART Interface: hardware flow control
I - - -
- / (Ignored)
O/Z - Z Z
SPI_SO OMS[2:0]=[1,0,1]: not used (tie to "0")
OMS[2:0]=[1,0,0]: SPI serial data output
B4 VDD_LPREG_OUT PO - - - - Low Power core regulator output
B5 TDI I/O I PU "C" 1 1 Serial Data Input (JTAG, IEEE 1149.1)
B6 VDD_LP PI - - - - Low Power supply
B7 VDD_CORE PI - - - - Digital core supply
C1 VDD_COREREG_O PO - - - - Digital core voltage regulator output
UT
C2 VDD_IO PI - - - - Digital I/O supply
P a d T y p e D e c s i r t p o i n C o m m e n s t
GND Chip Ground All signals are referred to this
P I Power In Supply to a voltage domain
P O Power Out Regulator Output
P I/O Power Out Supply to a voltage domain and regulator Output
I /O Digital Signal All Digital Pads are I /O Pads which are configured internally as required.
Pad - All are configured as Push-Pull e xcept those marked as OD (open drain)
- All have hysteresis by default, but is onl y mentioned when it is required for correct
system operation.
A I Analog Input
A O Analog Output
AI/O Analog Input/ Bidirectional analog pad.
Output
PU Internal Pull Up
PD Internal Pull
Down
SEMC Troubleshooting Manual
Top view (PCB footprint)
A7 B7 C7 D7 E7 F7 G7
A6 B6 C6 D6 E6 F6 G6
A5 B5 C5 D5 E5 F5 G5
A4 B4 C4 D4 E4 F4 G4
A3 B3 C3 D3 E3 F3 G3
A2 B2 C2 D2 E2 F2 G2
A1 B1 C1 D1 E1 F1 G1
0.3 0.25
mm mm
0.4 mm
3.7 mm
C3 HIF0 I/O Host Interface
I - - -
- / OMS[2:0]=[1,1,1]: not used (tie to "0")
I - - -
- / OMS[2:0]=[1,1,0]: not used (tie to "0")
2
I C I - - -
2
I C_SCL / OMS[2:0]=[1,0,1]: I 2 C clock
I - - -
- OMS[2:0]=[1,0,0]: not used (tie to "0")
C4 HIF1 I/O Host Interface
- / I - - - OMS[2:0]=[1,1,1]: not used (tie to "0")
I - - -
- / OMS[2:0]=[1,1,0]: not used (tie to "0")
2
I C I/O OD Z Z
I 2 C_SDA / OMS[2:0]=[1,0,1]: I 2 C data
I - - -
- OMS[2:0]=[1,0,0]: not used (tie to "0")
C5 TDO I/O O - Z Z Serial Data Output (JTAG, IEEE 1149.1)
C6 TCK I/O I PD "C" 0 0 Clock (JTAG, IEEE 1149.1)
C7 nTRST I/O I PD "A" 0 0 Reset Input (JTAG, IEEE 1149.1)
D1 VDD_COREREG_IN PI - - - - Digital core voltage regulator supply
D2 VSS_DIG GND - - - -
D3 OMS1 I/O I - - - Operational mode select / Bus interface select
D4 SYNC I I - - - Digital reference time pulse
D5 VSS_DIG GND - - - -
D6 TMS I/O I PU "C" 1 1 State Machine Control Signal (JTAG, IEEE 1149.1)
D7 VSS_DIG GND - - - -
E1 RTCCLK I/O I Hyst - - 32.768kHz clock signal input
E2 POWERON I/O I - 0 0 Power On signal to chip
E3 OMS0 I/O I - - - Operational mode select / Bus interface select
E4 VSS_LNA GND - - - -
E5 VSS_RF GND - - - -
E6 MIX_IN_PLUS AI AI - - - Differential mixer input
E7 VDD_CAP PI/O PI/O - (Z) (Z) RF Digital Supply Decoupling
F1 nINTR I/O O OD Z Z Interrupt request signal to host
F2 RX_HOLD I/O I - - - RX_HOLD signal (From host to indicate that the host is
transmitting)
I/O I Hyst 0 1
F3 nRESET Chip reset signal
F4 VDD_RFREG_IN PI - - - - RF voltage regulator input
F5 EXT_LNA_CTRL0 AI/O O - - - External LNA control
F6 MIX_IN_MINUS AI AI - - - Differential mixer input
F7 VDD_VCO PI/O PI/O - (Z) (Z) Buffer capacito r for VCO supply
G1 VDD_CORE PI - - - - Digital core supply
G2 OMS2 I/O I - - - Operational mode select
G3 VDD_CORE PI - - - - Digital core supply
G4 VSS_RF GND - - - -
G5 VDD_RF PI/0 - - - - RF Analog Supply Decoupling
G6 VSS AI AI - - -
G7 N.C. AO AO - - - This ball should be left unconnected
1221-7857 rev. 1
C702
100 (115)