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AK5349
(ADC)
INTERNAL
BLOCK
DIAGRAM
I
CLK
APD
NC
NO
OCLK
CLK
SCLK
L/IY
FSYNC
(
23
)
(
6
)
(
8
)
(
22
)
(
21
)
(
20
)
(
15
)
(
14
)
(
17
)
AK5349
(ADC)
PIN
FUNCTION
PIN NAME
I/O
FUNCTION
AINL+
I
L
CHANNEL ANALOG SIGNAL
INPUT (+)
AINL-
I
L
CHANNEL ANALOG SIGNAL
INPUT (-)
VREFIN
I
REFERENCE VOLTAGE INPUT
VA+
POWER SUPPLY FOR ANALOG CIRCUIT
(
+5V
)
AGND
GROUND FOR ANALOG CIRCUIT
APD
1
ANALOG POWER DOWN
(
"H*
LEVEL ACTIVE)
ACAL
I
ANALOG CALIBRATION
NC
I
NO
CONNECTION
DCAL
0
DIGITAL CALIBRATION
DPD
I
DIGITAL POWER DOWN
TST
I
TEST
CMODE
I
CLOCK MODE
"L":
CLK=256fs (12.288MHz fs=48KHz)
"H":
CLK=384fs (18.432MHz fs=48KHz)
SMODE
I
INTERFACE CLOCK
I/O
SELECT
"L":
SLAVE MODE
(
L/R.
SCLK
&
FSYNC*.
INPUT
)
"H":
MASTER MODE
(
L/R.
SCLK
& FSYNC: OUTPUT
)
L/R
I/O
L/R CLOCK
SLAVE
MODE: fs
CLOCK
INPUT
MASTER
MODE: fs
CLOCK OUTPUT
SCLK
I/O
SERIAL
DATA CLOCK
SLAVE
MODE: fs
CLOCK
INPUT
MASTER
MODE: fs CLOCK
OUTPUT
SDATA
0
SERIAL
DATA OUTPUT
FSYNC
I/O
FRAME SYNCHRONIZED CLOCK
SLAVE
MODE:
CLOCK
INPUT
MASTER
MODE: CLOCK OUTPUT
VD+
POWER SUPPLY FOR DIGITAL CIRCUIT
(
+5V
)
DGND
GROUND FOR DIGITAL CIRCUIT
CLK
I
MASTER CLOCK
INPUT
CMODE="H": 384fs
CMODE="L": 256fs
OCLK
0
128fs CLOCK OUTPUT
NC
NO
CONNECTION
I
CLK
I
128fs CLOCK INPUT
VL+
POWER SUPPLY FOR LOGIC CIRCUIT
(
+5V
)
LGND
GROUND FOR LOGIC CIRCUIT
VREF
0
REFERENCE VOLTAGE OUTPUT
2.56V
(
VA+ = +5V
)
AINR+
I
R
CHANNEL ANALOG SIGNAL
INPUT (-)
R
CHANNEL ANALOG SIGNAL
INPUT (+>
19

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