7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Architecture
7.3 MT8222 Video/Audio processor
Notes:
•
Only new circuits (circuits that are not published recently)
are described.
•
Figures can deviate slightly from the actual situation, due
to different set executions.
•
For a good understanding of the following circuit
descriptions, please use the wiring, block (see
chapter
9. Block
Diagrams) and circuit diagrams (see
chapter
10. Circuit Diagrams and PWB
necessary, you will find a separate drawing for clarification.
7.1
Introduction
The RAM1.0L LA chassis is using the MT8222 video and audio
processor.
B /L IN V E R TE R
M A IN
P O W E R
S UP P L Y
BL O C K
P /I b o a rd
Power
Video &
control signal
Analogue Audio
Layouts). Where
LC D PA N E L
(1 9 2 0 × 1 0 8 0 )
M a in b o a rd
3V 3
5V
5 V
D C
D C/DC
1V 8
conversion
1V 2
12 V
D C
5V 0
SPI F L A SH (4M B )
M X25L3205D M
BL on/off
PWM
D D R 2 256M b × 2
NT5TU32M 16 CG-25C
POK
BL boost
EDID
EDID
EDID
Figure 7-1 Architecture of RAM1.0L LA
Circuit Descriptions
7.1.1
Implementation
Key components of this chassis are:
•
MT8222 scaler
•
HFT-8-13F2 (Argentina) tuner
•
M3953M/M9370M (Argentina) saw filter
•
TDA9885TS IF demultiplexer
•
TPA3101D2 audio amplifier
•
TL2428MC T-CON IC
7.1.2
RAM1.0L LA Architecture Overview
•
For details about the chassis diagrams refer to
chapter
10. Circuit Diagrams and PWB
overview of the RAM1.0L LA architecture can be
found in
Figure
I.R. RE C E IV E R
K E Y P A D
M ini-LVDS
T C O N
EEPR O M
TL2428MC
24C 04
S c a le r c h ip
MTK
MT8222AMMU for FHD
EEPR O M
Audio sw itch
24C 32
HEF4052
X1
X1
X2
RAM1.0L LA
7.
Layouts. An
7-1.
L
R
A udio A m p
C lass-D
(T P A 3101D 2)
IF Deco d er
TD A 9885
C VBS
SIF
S A W
SIF
F ilter
R /L
An alo g
T u n er
18930_210_100310.eps
EN 31
VIF
S A W
F ilter
IF
100310
2010-Jul-02