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VIA Technologies VT82C42 Operation Manual

Keyboard controller
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VT82C42
K
C
EYBOARD
ONTROLLER
Preliminary Release
DATE : November 22, 1995
VIA TECHNOLOGIES, INC.

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Summary of Contents for VIA Technologies VT82C42

  • Page 1 VT82C42 EYBOARD ONTROLLER Preliminary Release DATE : November 22, 1995 VIA TECHNOLOGIES, INC.

  • Page 2: Copyright Notice

    All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document.

  • Page 3: General Overview

    PS/2 mode. Otherwise, the VT82C42 will remain in AT mode. If the VT82C42 is in AT mode after the self test, then it will drive P24 and P25 low with all other ports high. If the VT82C42 is in PS/2 mode, then it will drive P24, P25, P22, and P27 low with all other ports high. The VT82C42 will not change its driving value until it receives the command "AA"...
  • Page 4 The host can program the output port (P20-P23 in AT mode, or P20-P21 in PS/2 mode) or in-out port (P10- P15 in AT mode, or P12-P15 in PS/2 mode) by issuing a command to the command register on the VT82C42.
  • Page 5 VT82C42 VIA Technologies, Inc. 4. Register Table 1. Status register: read only (with A0 = 1, CS# = 0, RD# = 0, WR# = 1) Bit0 : OBF 1 means output buffer is full, 0 means output buffer is empty.

  • Page 6: Design Example

    VT82C42 VIA Technologies, Inc. number. B0h : write 0 to P10. B1h : write 0 to P11. B2h : write 0 to P12. B3h : write 0 to P13. B4h : write 0 to P22. B5h : write 0 to P23.
  • Page 7 VT82C42 VIA Technologies, Inc. 7406 Keyboard Clock Keyboard Data 7407 Fig 2. 2. To work with PS2 mode mother board. 7406 Mouse Data 7406 Keyboard Data 7406 Keyboard Clock 7406 Mouse Clock Fig 3.
  • Page 8 Ground. 1. Description for Table 4 RESET# is active low and is only an input pin. VT82C42 requires 10 clocks before RESET# goes to high to have the chip go to a known state. Pins WR#, RD#, CS# and A are all input only pins and must activate for at least one clock cycle width to be recognised by the VT82C42.
  • Page 9 MSLKMD is the mouse lock enable pin. When this pin is tied low, the Mouse Lock mode is enabled, otherwise the Mouse Lock mode is disabled. XTAL1, XTAL2 is the clocking source input of VT82C42, it can be implemented as in the figure 5. or figure 6. underneath:...
  • Page 10 XTAL1 CLOCK (1-12 MHz) XTAL2 Figure 6. Clocking from other clock source for VT82C42 2. A transmission from Keyboard Controller to external device * bitp means parity bit, bits means stop bit. * CLOCK is driven by external device except the leading 250µs & ending 60µs low time.

  • Page 11: Pin Assignments

    VT82C42 VIA Technologies, Inc. 7. Pin Assignments PLCC 44-Pin Configuration RESET XTAL1 TEST1 TH_SS XTAL2 TEST0 44 43 42 41 40 TL_EA SYNC TH_SSPP 18 19 20 21 22 23 24 25 26 27 28 NC P TH_PROG Fig 9.
  • Page 12 VT82C42 VIA Technologies, Inc. 8. Package Diagrams 44-Pin PLCC Dimension Diagram .045 .004 Fig 11. 44-Pin Quad PLCC (Q) Talbe 5. Dimension Minimum Typical Maximum Units 0.180 inches 0.020 inches 0.010 inches 0.685 0.690 0.695 inches 0.650 0.650 0.656 inches 0.590...
  • Page 13 VT82C42 VIA Technologies, Inc. 0.01 Fig 12. 40-Pin P-DIP Table 6. Dimension Minimum Typical Maximum Units 2.040 2.050 2.060 inches 1.530 1.540 1.550 inches 0.065 0.070 0.075 inches 0.546 0.550 0.554 inches 0.550 0.554 0.558 inches 0.130 0.150 0.170 inches 0.600...

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