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DV-505/DVF-4050/-S
Block Diagram for D/A Converter
BCK
LRCK
DATA
ML
MC
MDI
SCK
64 Bit SDRAM : HY57V651620B(IC301)
Pin No.
Pin Name
38
37
19
20,21
BA0,BA1
22~26
29~35
16,17,18
WE,CAS,RAS
15,39
LDQM,UDQM
2,4,5,7,8,10
11,13,42,44
DQ0~DQ15
45,47,48,50
1,3,9,14,27
VCC/VCC Q
43,49
10
VSS/VSS Q
36,40
Flash Memory : M29F400T-90N1(IC401)
Pin No.
Pin Name
25,24~16,8~1
29,31,33,35
DQ0~DQ7
38,40,42,44
30,32,34,36
DQ8~DQ14
39,41,43
45
26
28
11
12
15
47
37
27,46
8
CIRCUIT DESCRIPTION
Serial
Input
I/F
8X
Oversampling
Digital Filter
with
Function
Controller
Function
Control
I/F
System Clock
System
Clock
Zero Detect
Manager
I/O
The system clock input. all other inputs are registered to the SDRAM
CLK
I
on the rising edge of CLK
Controls internal clock signal and when deactivated,the SDRAM
CKE
-
will be one of the states among power down, suspend or self refresh.
CS
-
Enables or disables all inputs except CLK, CKE, and DQM.
Selects bank to be activated during RAS activity.
-
Selects bank to be read/written during CAS activity.
Row address : RA0~RA11, Column address : CA0~CA7
A0~A11
-
Auto-precharge flag : A10
-
WE, CAS and RAS define the operation.
I/O
Controls output buffers in read mode and masks input data in write mode.
I/O
Multiplexed data input/output pin.
-
Power supply for internal circuits and input buffers.
-
Ground terminal.
NC
-
Unused.
I/O
A0~A18
I
Address Inputs
I/O
Data Input/Outputs, Command Inputs
I/O
Data Input/Outputs
DQ15
I/O
Data Input/Outputs or Address input
CE
-
Chip Enable
QE
-
Output Enable
WE
-
Write Enable
RP
-
Reset/Block Temporary Unprotect
RY/BY
o
Ready/Busy/Output
BYTE
-
Byte/Word Organization
VCC
-
Supply Voltage
VSS
-
Ground
DAC
Enhanced
Multi-level
Delta-Sigma
modulator
DAC
Power Supply
Description
Description
Vout L
Output Amp and
Low-pass Filter
Vcom
Output Amp and
Low-pass Filter
Vout R
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