LG 55UF6800 Service Manual page 47

[51P Vx1
output wafer]
51pin_Wafer
P7100
SP14-11592-01-51Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TXDAP7_L
TXDAN7_L
TXDAP6_L
TXDAN6_L
TXDAP5_L
TXDAN5_L
TXDAP4_L
TXDAN4_L
TXDAP3_L
TXDAN3_L
TXDAP2_L
TXDAN2_L +3.3V_NORMAL
3D&L_DIM_EN_Micom
R7106
1K
TXDAP1_L
+3.3V_NORMAL
TXDAN1_L
3D&L_DIM_EN_Micom
R7104
L_DIM_EN_pulldown
10K
R7107
OPT
TXDAP0_L
1K
TXDAN0_L
M+ MODULE : low
LOCKAn_IN *Pin30(DATA_FORMAT)
HIGH : 2 DIVISION
HTPDAn_IN
LOW : NON DIVISION
Module_LGD_SHARP_CSHOT
R7101 10K
OPT
*Pin31(BIT_SEL)
R7102 10K HIGH or NC : 10Bit
LOW : 8Bit
R7108 0
3D&L_DIM_EN
OPT
*Pin38
CSOT, LGD60Hz,INX: N/C
SHARP,LGD120Hz: GND
GPLUS : PWM_TIN
Module_LGD120Hz_SHARP
R7123 10K
R7113 0
PWM_TIN
Module_MPLUS
PANEL_VCC
L7100
MLB-201209-0120P-N2
51pin_12V
C7100 C7101
10uF 10uF
25V 25V
51pin_12V 51pin_12V
+1.8V
LOCKAn_HTPDAn_3.3VPullup
HTPDAn_Video
LOCKAn_HTPDAn_3.3VPullup
HTPDAn_OSD
R174
R173
10K 10K LOCKAn_IN
*moved from SHT1.
+1.8V
LOCKAn_HTPDAn_3.3VPullup
LOCKAn_HTPDAn_3.3VPullup
HTPDAn_IN
D
DIODES_LGD/INX_Module_TCON_I2C_EN_FET(SUB)
Q7100-*1
G
2N7002K
EBK42767801
R7125 0
3D&L_DIM_EN S
TCON_I2C_EN
+3.3V_NORMAL
EBK62072501
Module_LGD_INX_CSHOT_MPLUS
R7121 0
R7115
4.7K
Q7100
40_INCH_INX_I2C_PULL_UP
2N7002KA
KEC_LGD/INX_Module_TCON_I2C_EN_FET(MAIN)
R7119
Module_LGD_INX_CSHOT_MPLUS 33 OPT
AR7101
0
1/16W
TCON_I2C_EN
+3.3V_NORMAL
Module_LGD_INX_CSHOT_MPLUS
R7122 0
R7116
I2C_SDA6
4.7K
40_INCH_INX_I2C_PULL_UP
Q7101
2N7002KA
EBK62072501
KEC_LGD/INX_Module_TCON_I2C_EN_FET(MAIN)
R7120
33 OPT
+3.3V_NORMAL
M+ MODULE
*Pin36(GPLUS_MODE)
R7109 HIGH : High luminance
10K
LOW or NC : Low Power
OPT LM14A : INTERNAL PULL-UP.
R7126 0
DATA_FORMAT_1_SOC
Module_MPLUS
Module_LGD120Hz
LGD_Module_120Hz
AR7100
R7110
0
10K
1/16W Data_Format_1
Data Input Format[1:0]
*Mode 1 (NON Division)
Data_Format_0
- Data Format 0(Pin37) = Low
Data Format 1(Pin36) = Low
+3.3V_NORMAL
*Mode 3 (4 Division)
- Data Format 0(Pin37) = Low
Data Format 1(Pin36) = High
R7111
10K
OPT
R7100 0
PWM_TOUT
Module_MPLUS
Module_LGD120Hz_MPLUS
R7112
10K
+3.3V_NORMAL
LOCKAn_HTPDAn_3.3VPullup
LOCKAn_HTPDAn_3.3VPullup R7136
R7132
10K
10K
LOCKAn
LOCKAn_HTPDAn_3.3VPullup
R7134 C
10K
B Q7105
R7128 2N3904S
KEC_LOCKAn_HTPDAn_3.3VPullup_TR
10K
E
C C
R7130
100
B Q7103 B Q7105-*1
2N3904S MMBT3904(NXP)
KEC_LOCKAn_HTPDAn_3.3VPullup_TR NXP_LOCKAn_HTPDAn_3.3VPullup_TR
E E
C
B Q7103-*1
MMBT3904(NXP)
NXP_LOCKAn_HTPDAn_3.3VPullup_TR
E
+3.3V_NORMAL
LOCKAn_HTPDAn_3.3VPullup
LOCKAn_HTPDAn_3.3VPullup R7135
R7131
10K
10K
HTPDAn
LOCKAn_HTPDAn_3.3VPullup
R7133 C
10K
B Q7104
R7127 2N3904S
KEC_LOCKAn_HTPDAn_3.3VPullup_TR
10K
E
C C
R7129
100
B Q7102 B Q7104-*1
2N3904S MMBT3904(NXP)
KEC_LOCKAn_HTPDAn_3.3VPullup_TR NXP_LOCKAn_HTPDAn_3.3VPullup_TR
E E
C
B Q7102-*1
MMBT3904(NXP)
NXP_LOCKAn_HTPDAn_3.3VPullup_TR
E
I2C_SCL6
D
DIODES_LGD/INX_Module_TCON_I2C_EN_FET(SUB)
Q7101-*1
G
2N7002K
EBK42767801
S
LM14A
Vx1 51P
BSD-15Y-LM14A-071_00-HD
2015-01-29
71