LG 86UH9500 Service Manual page 40

VREF_M0_0
IC101
VREF_M0_1
LGE1312(M16)
A22
M0_DDR_VREF_0
A2
M0_DDR_VREF_1
E13
M0_DDR_A0
M0_DDR_A0
E9
M0_DDR_A1 M0_DDR_A1
E15
M0_DDR_A2
M0_DDR_A2
E17
M0_DDR_A3 M0_DDR_A3
D7
M0_DDR_A4 M0_DDR_A4
D16
M0_DDR_A5 M0_DDR_A5
E7
M0_DDR_A6 M0_DDR_A6
E16
M0_DDR_A7
M0_DDR_A7
D8
M0_DDR_A8 M0_DDR_A8
E14
M0_DDR_A9
M0_DDR_A9
D6
M0_DDR_A10 M0_DDR_A10
D9
M0_DDR_A11
M0_DDR_A11
D10
M0_DDR_A12 M0_DDR_A12
D14
M0_DDR_A13
M0_DDR_A13
E8
M0_DDR_A14
M0_DDR_A14
E18
M0_DDR_A15/M0_DDR_CS1
D17
M0_DDR_BA0 M0_DDR_BA0
E6
M0_DDR_BA1 M0_DDR_BA1
D13
M0_DDR_BA2 M0_DDR_BA2
C8
M0_DDR_U_CLKP M0_U_CLK
B8
M0_U_CLKN
M0_DDR_U_CLKN
C17
M0_DDR_D_CLKP M0_D_CLK
B17
M0_D_CLKN
M0_DDR_D_CLKN
E10
M0_DDR_CKE M0_DDR_CKE
E19
M0_DDR_ODT M0_DDR_ODT
D19
M0_DDR_RASN
M0_DDR_RASN
D18
M0_DDR_CASN M0_DDR_CASN
D11
M0_DDR_WEN M0_DDR_WEN
D15
M0_DDR_RESET_N M0_DDR_RESET_N
B18
M0_DDR_DQS0 M0_DDR_DQS0
C18
M0_DDR_DQS_N0
M0_DDR_DQS_N0
B16
M0_DDR_DQS1 M0_DDR_DQS1
A16
M0_DDR_DQS_N1
M0_DDR_DQS_N1
B9
M0_DDR_DQS2 M0_DDR_DQS2
C9
M0_DDR_DQS_N2
M0_DDR_DQS_N2
B7
M0_DDR_DQS3 M0_DDR_DQS3
A7
M0_DDR_DQS_N3
M0_DDR_DQS_N3
A15
M0_DDR_DM0 M0_DDR_DM0
A18
M0_DDR_DM1 M0_DDR_DM1
A6
M0_DDR_DM2 M0_DDR_DM2
A9
M0_DDR_DM3
M0_DDR_DM3
B20
M0_DDR_DQ0
M0_DDR_DQ0
B13
M0_DDR_DQ1 M0_DDR_DQ1
C21
M0_DDR_DQ2
M0_DDR_DQ2
C14
M0_DDR_DQ3 M0_DDR_DQ3
A21
M0_DDR_DQ4
M0_DDR_DQ4
A13
M0_DDR_DQ5
M0_DDR_DQ5
B21
M0_DDR_DQ6
M0_DDR_DQ6
C13
M0_DDR_DQ7
M0_DDR_DQ7
B14
M0_DDR_DQ8 M0_DDR_DQ8
B19
M0_DDR_DQ9
M0_DDR_DQ9
C15
M0_DDR_DQ10 M0_DDR_DQ10
C20
M0_DDR_DQ11
M0_DDR_DQ11
C16
M0_DDR_DQ12 M0_DDR_DQ12
A19
M0_DDR_DQ13
M0_DDR_DQ13
B15
M0_DDR_DQ14 M0_DDR_DQ14
C19
M0_DDR_DQ15
M0_DDR_DQ15
B11
M0_DDR_DQ16 M0_DDR_DQ16
C5
M0_DDR_DQ17
M0_DDR_DQ17
C12
M0_DDR_DQ18
M0_DDR_DQ18
B4
M0_DDR_DQ19
M0_DDR_DQ19
A12
M0_DDR_DQ20
M0_DDR_DQ20
A4
M0_DDR_DQ21 M0_DDR_DQ21
B12
M0_DDR_DQ22
M0_DDR_DQ22
C4
M0_DDR_DQ23 M0_DDR_DQ23
B5
M0_DDR_DQ24
M0_DDR_DQ24
B10
M0_DDR_DQ25 M0_DDR_DQ25
C6
M0_DDR_DQ26
M0_DDR_DQ26
C11
M0_DDR_DQ27 M0_DDR_DQ27
C7
M0_DDR_DQ28
M0_DDR_DQ28
A10
M0_DDR_DQ29 M0_DDR_DQ29
B6
M0_DDR_DQ30
M0_DDR_DQ30
C10
M0_DDR_DQ31
M0_DDR_DQ31
A3 R401 240
M0_DDR_ZQCAL
1%
E11
M0_DDR_CS0 M0_DDR_CS0
D5
M0_RET DDR_RET
Add CS signal for 2T Mode &
RET signal for Instant On
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
+1.5V_DDR +1.5V_DDR
VREF_M0_1
VREF_M0_0
M0_D_CLK M0_U_CLK
R405
R410
100
100
M0_D_CLKN M0_U_CLKN
+1.5V_DDR
+1.5V_DDR +1.5V_DDR
M0_0_VREFCA M0_1_VREFCA
M0_DDR_RESET_N
+1.5V_DDR +1.5V_DDR
M0_1_VREFDQ
M0_0_VREFDQ
+1.5V_DDR
R420
22
DDR_RET
5%
C
R404
Q401
10K
B
INSTANT_BOOT MMBT3904(NXP)
E
M0_0_VREFCA
EAN64028101
IC401
H5TQ4G63CFR-TEC
M0_0_VREFDQ
DDR3
4Gbit
N3 M8
A0
M0_DDR_A0 VREFCA
(x16)
P7
M0_DDR_A1 A1
P3
M0_DDR_A2 A2
N2 H1
M0_DDR_A3 A3 VREFDQ
P8
M0_DDR_A4 A4
P2
A5
M0_DDR_A5 R418
R8 L8
M0_DDR_A6 A6
ZQ
R2
240
A7
M0_DDR_A7
1%
T8
M0_DDR_A8 A8
R3 B2
A9
M0_DDR_A9 VDD_1
L7 D9
M0_DDR_A10 A10/AP VDD_2
R7 G7
A11
M0_DDR_A11 VDD_3
N7 K2
M0_DDR_A12 A12/BC VDD_4
T3 K8
M0_DDR_A13 A13
VDD_5
T7 N1
M0_DDR_A14 A14 VDD_6
M7 N9
NC_5
VDD_7
R1
VDD_8
M2 R9
M0_DDR_BA0 BA0
VDD_9
N8
M0_DDR_BA1 BA1
M3
M0_DDR_BA2 BA2
A1
VDDQ_1
J7 A8
M0_D_CLK CK
VDDQ_2
K7 C1
CK
M0_D_CLKN VDDQ_3
K9 C9
M0_DDR_CKE CKE VDDQ_4
D2
VDDQ_5
L2 E9
M0_DDR_CS0 CS VDDQ_6
K1 F1
M0_DDR_ODT
ODT VDDQ_7
C413 0.1uF 16V
J3 H2
M0_DDR_RASN RAS VDDQ_8
K3 H9 C414 0.1uF 16V
M0_DDR_CASN
CAS VDDQ_9
L3
M0_DDR_WEN WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3
M0_DDR_DQS0
DQSL
G3
M0_DDR_DQS_N0 DQSL
C7 A9
M0_DDR_DQS1 DQSU VSS_1
B7 B3
M0_DDR_DQS_N1 DQSU VSS_2
E1
VSS_3
E7 G8
M0_DDR_DM0 DML VSS_4
D3 J2
M0_DDR_DM1
DMU VSS_5
J8
VSS_6
E3 M1
M0_DDR_DQ0
DQL0 VSS_7
F7 M9
M0_DDR_DQ1 DQL1 VSS_8
F2 P1
M0_DDR_DQ2
DQL2 VSS_9
F8 P9
M0_DDR_DQ3 DQL3 VSS_10
H3 T1
M0_DDR_DQ4 DQL4
VSS_11
H8 T9
M0_DDR_DQ5 DQL5 VSS_12
G2
M0_DDR_DQ6 DQL6
H7
M0_DDR_DQ7 DQL7
B1
VSSQ_1
D7 B9
M0_DDR_DQ8
DQU0 VSSQ_2
C3 D1
M0_DDR_DQ9 DQU1 VSSQ_3
C8 D8
M0_DDR_DQ10
DQU2 VSSQ_4
C2 E2
M0_DDR_DQ11 DQU3 VSSQ_5
A7 E8
M0_DDR_DQ12
DQU4 VSSQ_6
A2 F9
M0_DDR_DQ13 DQU5 VSSQ_7
B8 G1
M0_DDR_DQ14
DQU6 VSSQ_8
A3 G9
M0_DDR_DQ15 DQU7 VSSQ_9
DDR_512MB_HYNIX_2133
INSTANT BOOT MODE
- '0' : Normal, Default
(Internal Pull-down)
- '1': Instant Boot
EAN64028101
IC402
H5TQ4G63CFR-TEC
DDR3
N3
4Gbit
M0_DDR_A0 A0 VREFCA
P7
(x16)
M0_DDR_A1 A1
P3
M0_DDR_A2
A2
N2
M0_DDR_A3 A3 VREFDQ
P8
+1.5V_DDR M0_DDR_A4
A4
P2
M0_DDR_A5 A5
R8
M0_DDR_A6 ZQ
A6
R2
M0_DDR_A7 A7
T8
M0_DDR_A8
A8
R3
M0_DDR_A9 A9 VDD_1
L7
M0_DDR_A10 A10/AP VDD_2
R7
M0_DDR_A11 A11 VDD_3
N7
M0_DDR_A12 A12/BC VDD_4
T3
M0_DDR_A13
A13 VDD_5
T7
M0_DDR_A14 A14 VDD_6
M7
NC_5 VDD_7
VDD_8
M2
M0_DDR_BA0
BA0 VDD_9
N8
M0_DDR_BA1 BA1
M3
M0_DDR_BA2
BA2
VDDQ_1
J7
M0_U_CLK
CK VDDQ_2
K7
M0_U_CLKN CK VDDQ_3
K9
M0_DDR_CKE CKE VDDQ_4
VDDQ_5
L2
M0_DDR_CS0 CS VDDQ_6
K1
M0_DDR_ODT
ODT VDDQ_7
J3
M0_DDR_RASN RAS VDDQ_8
K3
M0_DDR_CASN
CAS VDDQ_9
L3
M0_DDR_WEN WE
NC_1
T2
M0_DDR_RESET_N RESET NC_2
NC_3
NC_4
F3
M0_DDR_DQS2
DQSL
G3
M0_DDR_DQS_N2 DQSL
C7
M0_DDR_DQS3 DQSU VSS_1
B7
M0_DDR_DQS_N3 DQSU VSS_2
VSS_3
E7
M0_DDR_DM2 DML VSS_4
D3
M0_DDR_DM3
DMU VSS_5
VSS_6
E3
M0_DDR_DQ16
DQL0 VSS_7
F7
M0_DDR_DQ17 DQL1 VSS_8
F2
M0_DDR_DQ18
DQL2 VSS_9
F8
M0_DDR_DQ19 DQL3 VSS_10
H3
M0_DDR_DQ20 DQL4
VSS_11
H8
M0_DDR_DQ21 DQL5 VSS_12
G2
M0_DDR_DQ22 DQL6
H7
M0_DDR_DQ23 DQL7
VSSQ_1
D7
M0_DDR_DQ24
DQU0 VSSQ_2
C3
M0_DDR_DQ25 DQU1 VSSQ_3
C8
M0_DDR_DQ26
DQU2 VSSQ_4
C2
M0_DDR_DQ27 DQU3 VSSQ_5
A7
M0_DDR_DQ28
DQU4 VSSQ_6
A2
M0_DDR_DQ29 DQU5 VSSQ_7
B8
M0_DDR_DQ30
DQU6 VSSQ_8
A3
M0_DDR_DQ31 DQU7 VSSQ_9
DDR_512MB_HYNIX_2133
EAN64108201 EAN64129401
IC401-*1 IC401-*2
K4B4G1646E-BCNB MT41K256M16LY-093:N
N3 M8 N3 M8
A0 VREFCA A0 VREFCA
P7 P7
A1 A1
P3 P3
A2 A2
N2 H1 N2 H1
A3 VREFDQ A3 VREFDQ
P8 P8
P2 A4 P2 A4
A5 A5
R8 L8 R8 L8
A6 ZQ A6 ZQ
R2 R2
A7 A7
T8 T8
A8 A8
R3 B2 R3 B2
A9 VDD_1 A9 VDD_1
L7 D9 L7 D9
A10/AP VDD_2 A10/AP VDD_2
R7 G7 R7 G7
A11 VDD_3 A11 VDD_3
N7 K2 N7 K2
A12/BC VDD_4 A12/BC VDD_4
T3 K8 T3 K8
A13 VDD_5 A13 VDD_5
N1 N1
VDD_6 VDD_6
M7 N9 M7 N9
NC_5 VDD_7 NC_5 VDD_7
R1 R1
VDD_8 VDD_8
M2 R9 M2 R9
VDD_9 VDD_9
N8 BA0 N8 BA0
BA1 BA1
M3 M3
BA2 BA2
A1 A1
VDDQ_1 VDDQ_1
J7 A8 J7 A8
CK VDDQ_2 CK VDDQ_2
K7 C1 K7 C1
CK VDDQ_3 CK VDDQ_3
K9 C9 K9 C9
CKE VDDQ_4 CKE VDDQ_4
D2 D2
VDDQ_5 VDDQ_5
L2 E9 L2 E9
CS VDDQ_6 CS VDDQ_6
K1 F1 K1 F1
ODT VDDQ_7 ODT VDDQ_7
J3 H2 J3 H2
RAS VDDQ_8 RAS VDDQ_8
K3 H9 K3 H9
CAS VDDQ_9 CAS VDDQ_9
L3 L3
WE WE
J1 J1
NC_1 NC_1
T2 J9 T2 J9
RESET NC_2 RESET NC_2
L1 L1
NC_3 NC_3
L9 L9
NC_4 NC_4
F3 T7 F3 T7
DQSL NC_6 LDQS A14
G3 G3
DQSL LDQS
C7 A9 C7 A9
DQSU VSS_1 UDQS VSS_1
B7 B3 B7 B3
DQSU VSS_2 UDQS VSS_2
E1 E1
VSS_3 VSS_3
E7 G8 E7 G8
DML VSS_4 LDM VSS_4
D3 J2 D3 J2
DMU VSS_5 UDM VSS_5
J8 J8
VSS_6 VSS_6
E3 M1 E3 M1
DQL0 VSS_7 DQ0 VSS_7
F7 M9 F7 M9
DQL1 VSS_8 DQ1 VSS_8
F2 P1 F2 P1
DQL2 VSS_9 DQ2 VSS_9
F8 P9 F8 P9
DQL3 VSS_10 DQ3 VSS_10
H3 T1 H3 T1
DQL4 VSS_11 DQ4 VSS_11
H8 T9 H8 T9
DQL5 VSS_12 DQ5 VSS_12
G2 G2
DQL6 DQ6
H7 H7
DQL7 DQ7
B1 B1
VSSQ_1 VSSQ_1
D7 B9 D7 B9
DQU0 VSSQ_2 DQ8 VSSQ_2
C3 D1 C3 D1
DQU1 VSSQ_3 DQ9 VSSQ_3
C8 D8 C8 D8
DQU2 VSSQ_4 DQ10 VSSQ_4
C2 E2 C2 E2
DQU3 VSSQ_5 DQ11 VSSQ_5
A7 E8 A7 E8
DQU4 VSSQ_6 DQ12 VSSQ_6
A2 F9 A2 F9
DQU5 VSSQ_7 DQ13 VSSQ_7
B8 G1 B8 G1
DQU6 VSSQ_8 DQ14 VSSQ_8
A3 G9 A3 G9
DQU7 VSSQ_9 DQ15 VSSQ_9
DDR_512MB_SS_2133 DDR_512MB_MICRON_2133
M16
M16 DDR3-M0
PAGE 4
M0_1_VREFCA
M0_1_VREFDQ
M8
H1
+1.5V_DDR
R419
L8
240
1%
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
C429
H2 0.1uF 16V
H9 C430 0.1uF 16V
J1
J9
L1
L9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
EAN64108201 EAN64129401
IC402-*1 IC402-*2
K4B4G1646E-BCNB MT41K256M16LY-093:N
N3 M8 N3 M8
A0 VREFCA A0 VREFCA
P7 P7
A1 A1
P3 P3
A2 A2
N2 H1 N2 H1
A3 VREFDQ A3 VREFDQ
P8 P8
P2 A4 P2 A4
A5 A5
R8 L8 R8 L8
A6 ZQ A6 ZQ
R2 R2
A7 A7
T8 T8
A8 A8
R3 B2 R3 B2
A9 VDD_1 A9 VDD_1
L7 D9 L7 D9
A10/AP VDD_2 A10/AP VDD_2
R7 G7 R7 G7
A11 VDD_3 A11 VDD_3
N7 K2 N7 K2
A12/BC VDD_4 A12/BC VDD_4
T3 K8 T3 K8
A13 VDD_5 A13 VDD_5
N1 N1
VDD_6 VDD_6
M7 N9 M7 N9
NC_5 VDD_7 NC_5 VDD_7
R1 R1
VDD_8 VDD_8
M2 R9 M2 R9
VDD_9 VDD_9
N8 BA0 N8 BA0
BA1 BA1
M3 M3
BA2 BA2
A1 A1
VDDQ_1 VDDQ_1
J7 A8 J7 A8
CK VDDQ_2 CK VDDQ_2
K7 C1 K7 C1
CK VDDQ_3 CK VDDQ_3
K9 C9 K9 C9
CKE VDDQ_4 CKE VDDQ_4
D2 D2
VDDQ_5 VDDQ_5
L2 E9 L2 E9
CS VDDQ_6 CS VDDQ_6
K1 F1 K1 F1
ODT VDDQ_7 ODT VDDQ_7
J3 H2 J3 H2
RAS VDDQ_8 RAS VDDQ_8
K3 H9 K3 H9
CAS VDDQ_9 CAS VDDQ_9
L3 L3
WE WE
J1 J1
NC_1 NC_1
T2 J9 T2 J9
RESET NC_2 RESET NC_2
L1 L1
NC_3 NC_3
L9 L9
NC_4 NC_4
F3 T7 F3 T7
DQSL NC_6 LDQS A14
G3 G3
DQSL LDQS
C7 A9 C7 A9
DQSU VSS_1 UDQS VSS_1
B7 B3 B7 B3
DQSU VSS_2 UDQS VSS_2
E1 E1
VSS_3 VSS_3
E7 G8 E7 G8
DML VSS_4 LDM VSS_4
D3 J2 D3 J2
DMU VSS_5 UDM VSS_5
J8 J8
VSS_6 VSS_6
E3 M1 E3 M1
DQL0 VSS_7 DQ0 VSS_7
F7 M9 F7 M9
DQL1 VSS_8 DQ1 VSS_8
F2 P1 F2 P1
DQL2 VSS_9 DQ2 VSS_9
F8 P9 F8 P9
DQL3 VSS_10 DQ3 VSS_10
H3 T1 H3 T1
DQL4 VSS_11 DQ4 VSS_11
H8 T9 H8 T9
DQL5 VSS_12 DQ5 VSS_12
G2 G2
DQL6 DQ6
H7 H7
DQL7 DQ7
B1 B1
VSSQ_1 VSSQ_1
D7 B9 D7 B9
DQU0 VSSQ_2 DQ8 VSSQ_2
C3 D1 C3 D1
DQU1 VSSQ_3 DQ9 VSSQ_3
C8 D8 C8 D8
DQU2 VSSQ_4 DQ10 VSSQ_4
C2 E2 C2 E2
DQU3 VSSQ_5 DQ11 VSSQ_5
A7 E8 A7 E8
DQU4 VSSQ_6 DQ12 VSSQ_6
A2 F9 A2 F9
DQU5 VSSQ_7 DQ13 VSSQ_7
B8 G1 B8 G1
DQU6 VSSQ_8 DQ14 VSSQ_8
A3 G9 A3 G9
DQU7 VSSQ_9 DQ15 VSSQ_9
DDR_512MB_SS_2133 DDR_512MB_MICRON_2133
2015.02.09
4 26
LGE Internal Use Only