Onkyo DX-C390 Service Manual page 31

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q501 : LC78683E MP3 DECODER FOR CD
Continued from preceding page.
Pin No. Pin Name I/O
51 DV 4
DD
52 V
SS
53 MADRS7 O
54 MADRS6 O
55 MADRS5 O
56 MADRS4 O
57 MADRS3 O
58 MADRS2 O
59 MADRS1 O
60 MADRS0 O
61 DV 5
DD
62 V
SS
63 STREQ I/O
64 STCK I/O
65 STDAT I/O
66 FSYNC O
67 CRCF O
68 DV 6
DD
69 V
SS
70 WOK I
71 CNTOK O
72 OVF O
73 CMDOUT O
74 CMDIN I
75 CL I
76 CE I
77 INTB O
78 RESB I
79 DATAIN I
80 DATACK I
Notes: 1. Notes on unused pins.
Unused input pins must be connected to the ground level (0 V).
Unused output pins must be left open. Do not connect anything to these pins.
Unused I/O pins may either be connected to the ground level (0 V) or set to output mode and left open.
2. The corresponding power supply levels must be provided to all of the DV
corresponding power supply level must also be provided to DV
the supply levels.)
3. The TEST1 and TEST2 input pins must be connected to ground (0 V).
4. The I/O pins (MDAT0:15, STREQ, STCK, and STDAT) go to input mode after a reset.
5. After first applying the power supply levels, the RESB pin must be held low for at least 1 µs.
6. A 16.9344 MHz clock signal must be supplied to the CKIN pin by the CD DSP.
The LC78684E does not support the implementation of an oscillator circuit using an oscillator element.
Block
Digital I/O system power supply
Power supply
Ground
DRAM address output 7
DRAM address output 6
DRAM address output 5
DRAM address output 4
Memory interface
DRAM address output 3
DRAM address output 2
DRAM address output 1
DRAM address output 0
Internal logic system power supply
Power supply
GND
MP3 data request flag output (active high)
/DRAM data request flag input (CD-ROM mode, active high)
MP3 data transfer clock input
MP3 stream I/O
/DRAM data transfer clock output
MP3 serial data input
/DRAM serial data output
MP3 frame sync signal (active high)
MP3-dec
/Data continuity point detection complete flag (CD-DA mode, active high)
CRC check result output (CD-ROM data/CD-DA subcode data)
CD monitor
/DRAM data output enable signal output (active high)
Digital I/O system power supply
Power supply
GND
DRAM write enable input (CD-DA mode, active high)
/DRAM data request flag input
Data continuity point detection complete flag (CD-DA mode, active high)
CD-DA shockproof
/SYNC error monitor flag (MP3 mode, active high)/DRAM serial data output
and MP3 I/O
DRAM write interrupt flag (CD-DA mode, active high)
/Emphasis output flag (CD-DA and MP3 modes, active high)
/DRAM data transfer clock output
Serial command data output (n-channel open-drain output)
Serial command data input
Serial command clock input
Microcontroller
Command enable input (active high)
interface
Interrupt signal output (active low)
/DRAM write interrupt flag (CD-DA mode, active high)
System reset (active low)
Serial CD data input
CD IF
CD bit clock input
31 of 63
Function
1, DV 3, DV 4, DV
DD DD DD
2 and DV 5. (See the Allowable Operating Ranges specifications for
DD DD
DX-C390
6, and AV pins. The
DD DD