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The table below provides a summary of bit settings and operation.
PRTRG
FFM0
0
0
1
1
C0SRC
This bit allows the user to select the clock source for user Counter 0.
1 = Internal 10MHz oscillator
0 = External clock source input via CTR0CLK pin on 100p connector.
READ
15
14
13
12
-
-
-
INDX_GT
XTRIG
1 = External Trigger flip-flop has been set. This bit is write-cleared.
0 = External Trigger flip-flop reset. No trigger has been received.
INDX_GT
1 = Pre-trigger index counter has completed its count.
0 = Pre-trigger index counter has not been gated on or has not yet completed its count
ARM is set...
0
Via SW when
remaining count <1024
------------------------
Via SW immediately
1
Via SW immediately
0
Via SW when
remaining count <1024
------------------------
Via SW immediately
1
Via SW immediately
11
10
9
-
-
-
FIFO Mode
# Samples >1 FIFO
Normal Mode
----------------------------------
1/2 FIFO < # Samples < 1 FIFO
Normal Mode
# Samples <1/2 FIFO
Normal Mode
# Samples >1 FIFO
Pre-Trigger Mode
----------------------------------
1/2 FIFO < # Samples < 1 FIFO
Pre-Trigger Mode
# Samples <1/2 FIFO,
Pre-Trigger Mode
8
7
6
5
-
XTRIG
-
-
22
Sample CTR
Starts on...
ADHF
ADC Pacer
ADHF
XTRIG
4
3
2
1
-
-
-
-
.
0
-
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