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Related Manuals for Omega Engineering PCI-DAS1001
Summary of Contents for Omega Engineering PCI-DAS1001
- Page 1 User's Guide http://www.omega.com e-mail: info@omega.com PCI-DAS1001 PCI-DAS1002...
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Page 2: Table Of Contents
1.0 INTRODUCTION 2.0 INSTALLATION ........... . . 2.1 HARDWARE INSTALLATION . - Page 3 7.0 PCI-DAS1000 REGISTER DESCRIPTION 7.1 REGISTER OVERVIEW ..........7.2 BADR0 .
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Page 4: Introduction
The PCI-DAS1002 and PCI-DAS1001 are multifunction analog and digital I/O boards designed to operate in computers with PCI bus accessory slots. The boards provide 16 single-ended/8 differential analog inputs with sample rates as high as 150 KHz. The boards also provide two analog output channels, 24-bits of parallel digital I/O and three counters. The only difference between the boards are the analog input ranges. -
Page 5: Installation
2.1 HARDWARE INSTALLATION The PCI-DAS1001 and PCI-DAS1002 products are completely plug and play. Simply follow the steps shown below to install your PCI hardware. Turn your computer off, unplug it, open it up and insert the PCI board into any available PCI slot. -
Page 6: Run Instacal
2.3 RUN InstaCal Run the InstaCal program in order to test your board and configure it for run-time use. By configuring the board, you add information to the configuration file, cb.cfg, that is used by the Universal Library and other third-party data acquisition packages that use the Universal Library to access the board. -
Page 7: Hardware Connections
3.1 CONNECTOR PIN DIAGRAM The PCI-DAS1000 series employ a 100 pin I/O connector. Please make accurate notes and pay careful attention to wire connections. In a large system a misplaced wire may create hours of work ‘fixing’ problems that do not exist before the wiring error is found. -
Page 8: Analog Connections
4.1 ANALOG INPUTS Analog signal connection is one of the most challenging aspects of applying a data acquisition board. If you are an Analog Electrical Engineer then this section is not for you, but if you are like most PC data acquisition users, the best way to connect your analog inputs may not be obvious. -
Page 9: Differential Inputs
Differential Inputs Differential inputs measure the voltage between two distinct input signals. Within a certain range (referred to as the common mode range), the measurement is almost independent of signal source to PCI-DAS1000 ground variations. A differential input is also much more immune to EMI than a single-ended one. Most EMI noise induced in one lead is also induced in the other, the input only measures the difference between the two leads, and the EMI common to both is ignored. -
Page 10: System Grounds And Isolation
+13V +12V +11V +10V -10V -11V -12V -13V 4.1.2 System Grounds and Isolation There are three scenarios possible when connecting your signal source to your PCI-DAS1000 board. 1. The PCI-DAS1000 and the signal source may have the same (or common) ground. - Page 11 If either the AC or DC voltage is greater than 10 volts, do not connect the PCI-DAS1000 to this signal source. You are beyond the boards usable common mode range and will need to either adjust your grounding system or add special Isolation signal conditioning to take useful measurements. A ground offset voltage of more than 30 volts will likely damage the PCI-DAS1000 board and possibly your computer.
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Page 12: Wiring Configurations
Relying on the earth prong of a 120VAC for signal ground connections is not advised.. Different ground plugs may have large and potentially even dangerous voltage differentials. Remember that the ground pins on 120VAC outlets on different sides of the room may only be connected in the basement. This leaves the possibility that the “ground”... -
Page 13: Common Ground / Single-Ended Inputs
4.2.1 Common Ground / Single-Ended Inputs Single-ended is the recommended configuration for common ground connections. However, if some of your inputs are common ground and some are not, we recommend you use the differential mode. There is no performance penalty (other than loss of channels) for using a differential input to measure a common ground signal source. -
Page 14: Common Mode Voltage < +/-10V / Differential Inputs
4.2.4 Common Mode Voltage < +/-10V / Differential Inputs Systems with varying ground potentials should always be monitored in the differential mode. Care is required to assure that the sum of the input signal and the ground differential (referred to as the common mode voltage) does not exceed the common mode range of the A/D board (+/-10V on the PCI-DAS1000). -
Page 15: Isolated Grounds / Single-Ended Inputs
G N D W hen the voltage difference betw een signal source and A /D board gro und is large enough so the A /D board’s com m on m ode ran ge is exceeded, isolated sig nal conditioning m ust be added. S ystem w ith a La rge C om m on M ode Voltag e, 4.2.6 Isolated Grounds / Single-Ended Inputs Single-ended inputs can be used to monitor isolated inputs, though the use of the differential mode will increase your... - Page 16 G N D 1 0 K T he se g ro u n ds are 1 0 K is a rec o m m e nd e d v a lue . Yo u m ay s ho rt LL G N D to C H L ow e lec trica lly isolated .
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Page 17: Programming & Software Applications
5.0 PROGRAMMING & SOFTWARE APPLICATIONS Your PCI-DAS1000 is supported by the powerful Universal Library. We strongly recommend that you take advantage of the Universal Library as you software interface. The complexity of the the registers required for automatic calibration combined with the PCI BIOS's dynamic allocation of addresses and internal resources makes the PCI-DAS1000 series very challenging to program via direct register I/O operations. -
Page 18: Self-Calibration Of The Pci-Das1000
6.0 SELF-CALIBRATION OF THE PCI-DAS1000 The PCI-DAS1000 is shipped fully-calibrated from the factory with cal coefficients stored in nvRAM. At run time, these calibration factors are loaded into system memory and are automatically retrieved each time a different DAC/ADC range is specified. -
Page 19: Analog Outputs
6.1.2 Analog Outputs The calibration scheme for the Analog Out section is shown in Figure 2 below. This circuit is duplicated for both DAC0 and DAC1 Trim Dac Trim Dac Trim Dac Trim Dac Trim Dac Trim Dac Trim Dac Trim Dac Trim Dac Trim Dac... -
Page 20: Pci-Das1000 Register Description
7.1 REGISTER OVERVIEW PCI-DAS1000 operation registers are mapped into I/O address space. Unlike ISA bus designs, this board has several base addresses each corresponding to a reserved block of addresses in I/O space. As we mention in our programming chapter, we highly recommend customers use the Universal Library package. - Page 21 INT[1:0] General Interrupt Source selection bits. INTE Enables interrupt source selected via the INT[1:0] bits. 1 = Selected interrupt Enabled 0 = Selected interrupt Disabled EOAIE Enables End-of-Acquisition interrupt. Used during FIFO'd ADC operations to indicate that the desired sample size has been gathered. 1= Enable EOA interrupt 0 = Disable EOA interrupt EOACL...
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Page 22: Adc Channel Mux And Control Register
ADHFI Status bit of ADC FIFO Half-Full interrupt. Used during REP INSW operations. 1 = Indicates an ADC Half-Full interrupt has been latched. FIFO has been filled with more than 255 samples. 0 = Indicates an ADC Half-Full interrupt has not occurred. FIFO has not yet exceeded 1/2 of its total capacity. - Page 23 The following tables summarizes all possible Offset/Range configurations PCI-DAS1002 UNIBIP PCI-DAS1001 UNIBIP ADPS[1:0] These bits select the ADC Pacer Source. Maximum Internal/External Pacer frequency is 330KHz. Note: For ADPS[1:0] = 00 case, SW conversions are initiated via a word write to BADR2 + 0. Data is 'don't care.' READ Real-time, non-latched status of ADC End-of-Conversion signal.
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Page 24: Trigger Control/Status Register
7.3.3 TRIGGER CONTROL/STATUS REGISTER BADR1 + 4 This register provides control bits for all ADC trigger modes. A Read/Write register. WRITE C0SRC FFM0 TS[1:0] These bits select one-of-two possible ADC Trigger Sources: Note : TS[1:0] should be set to 0 while setting up Pacer source and count values. TGEN This bit is used to enable External Trigger function 1 = External rising-edge Digital Trigger enabled. - Page 25 The table below provides a summary of bit settings and operation. PRTRG FFM0 remaining count <1024 remaining count <1024 C0SRC This bit allows the user to select the clock source for user Counter 0. 1 = Internal 10MHz oscillator 0 = External clock source input via CTR0CLK pin on 100p connector. READ INDX_GT XTRIG...
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Page 26: Calibration Register
7.3.4 CALIBRATION REGISTER See "Calibrating The PCI-DAS1000" document for additional programming details. BADR1 + 6 This register controls all autocal operations. This is a Write-only register. WRITE CALEN CSRC2 CSRC1 CSRC0 SEL8800 This bit enables the 8-bit trim DACs for the following circuits: SEL7376 This bit latches the 7-bit serial data stream into the AD7376 digital potentiometer (10KOhm). -
Page 27: Dac Control/Status Register
7.3.5 DAC CONTROL/STATUS REGISTER BADR1 + 8 This register selects the DAC gain/range and update modes. This is a Write-only register. WRITE DAC1R1 DACEN This bit enables the Analog Out features of the board. 1 = DAC0/1 enabled. 0 = DAC0/1 disabled. The power-on state of this bit is 0. -
Page 28: Badr2 + 0
7.4 BADR2 The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear register. 7.4.1 ADC DATA REGISTER BADR2 + 0 ADC Data register. WRITE Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must be set to 00 via the ADPS[1:0] bits. -
Page 29: Badr3
7.5 BADR3 The I/O Region defined by BADR3 contains data and control registers for the ADC Pacer, Pre/Post-Trigger Counters, User Counters and Digital I/O bytes. The PCI-DAS1000 has two 8254 counter/timer devices. These are referred to as 8254A and 8254B and are assigned as shown below: Device 8254A 8254A... -
Page 30: Digital I/O Data And Control Registers
8254A COUNTER 2 DATA - ADC PACER DIVIDER UPPER BADR3 + 2 Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is fed to the clock input of Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a precision 10MHz oscillator source. - Page 31 DIO PORT C DATA BADR3 + 6 PORT C may be configured as an 8-bit port of either input or output, or it may be split into two independent 4-bit ports of input or output. When split into two 4-bit I/O ports, D[3:0] make up the lower nibble, D[7:4] comprise the upper nibble.
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Page 32: Index And User Counter 4 Data And Control Registers
7.5.3 INDEX and USER COUNTER 4 DATA AND CONTROL REGISTERS 8254B COUNTER 0 DATA - ADC PRE-TRIGGER INDEX COUNTER(or user counter 4) BADR3 + 8 READ/WRITE Counter 0 of the 8254B device is a shared resource on the PCI-DAS1000. When not in ADC pre-trigger mode, the clock, gate and output lines of Counter 0 are available to the user at the 100 pin connector as user counter 4. - Page 33 8254B CONTROL REGISTER BADR3 + Bh WRITE ONLY The control register is used to set the operating Modes of 8254B Counters 0,1 & 2. A counter is configured by writing the correct Mode information to the Control Register, then the proper count data must be written to the specific Counter Regis- ter.
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Page 34: Badr4 + 0
7.6 BADR4 The I/O Region defined by BADR4 contains the DAC0 and DAC1 data registers. 7.6.1 DAC0 DATA REGISTER BADR4 + 0 WRITE DAC0(11) Writing to this register will initiate data conversion on DAC0. If the MODE bit in BADR1+8 is set, writes to this register will provide a simultaneous update of both DAC0 and DAC1 with the data written to this regis- ter. -
Page 35: Electrical Specifications
(Typical specifications for 25 DegC unless otherwise specified.) 8.1 ANALOG INPUT SECTION A/D converter type Resolution Programmable ranges PCI-DAS1001 PCI-DAS1002 A/D pacing Burstmode A/D Trigger sources A/D Triggering Modes Digital: Pre-trigger: Data transfer Polarity Number of channels A/D conversion time... -
Page 36: Analog Output
8.2 ANALOG OUTPUT D/A type Resolution Number of channels Output Ranges D/A pacing Data transfer Offset error Gain error Differential nonlinearity Integral nonlinearity Monotonicity D/A Gain drift D/A Bipolar offset drift D/A Unipolar offset drift Throughput Settling time (to .01% of 10V step) Slew Rate Current Drive Output short-circuit duration... -
Page 37: Counter Section
8.4 COUNTER SECTION Counter type Configuration Clock input frequency High pulse width (clock input) Low pulse width (clock input) Gate width high or low Input low voltage Input high voltage Output low voltage Output high voltage 8.5 OTHER SPECIFICATIONS Power consumption +5V Operating (A/D converting to FIFO) Environmental Operating temperature range... -
Page 38: Ec Declaration Of Conformity
PCI-DAS1000 High speed analog I/O board for the PCI bus Part Number Description to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied according to the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents: EU EMC Directive 89/336/EEC: Essential requirements relating to electromagnetic compatibility.
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