Schematic Diagram - Yamaha RX-V2300 Service Manual

A B
SCHEMATIC DIAGRAM (DSP)
1
2
DIGITAL OUT INHIBIT
3.4
1
0.1 0.1
3
4.9 2 4.9 4.8 0
0.2 0.2
0
0.2 0.2
0.2 0.2
0.2 0.2
4.8 0
4.9
4
0.1 0.1
3.4 0.9 0.1
6
5 0.8 0.1
4.9
0.9 0.1
0
0.9 0.1
2.3
3
0 2.3
3.9 1.9 2.1
1.5
0
~ ~
4.9
~ ~
~ ~
~ ~
4.8 0
3.9
0
4.9
3.9
0
4.9 4.9
4.9 14
13
8 11 3.5
3
1 0 0
12
2 4.9
0 0 7
0 0 0
4
4
0
0
3.9
0 0
4.9
5
0
9
7 8
0 0.1
0 4.9
10
6
DUTY CORRECTOR
4.9 4.9
14 14
0 0 0.1
3.1 7 0 7 4.9
2.6 0.5
0
0
0
DIGITAL IN
0 0 0
0.5 4.9
3.1 0
2.6
5 0
LEVEL CONVERT & SIGNAL DETECT
0.1 0.1 0 0
4.9 4.9
3.4 3.4 3.4 4.9
3.4 0 3.4 0
3.4 0 3.4 3.4
3.4 3.4 3.4 3.4
3.4 3.4 3.5 3.4
6
3.4 0
3.5 3.4
3.5 3.4 3.4 3.4
3.5 0 3.4 3.4
3.4 3.4 0.1
0 3.4 3.4
0
3.4 3.4 3.4
4.9 3.4 3.4
0
0 3.4 3.4
3.4
0 3.4
0
256K
3.4
0.1 0
SRAM
3.4 3.4
3.4
0
3.4 3.4
3.4
3.4 0
3.4 3.4
3.4
3.4
4M
FLASH
7
IC528: MX29F400BTC-70 IC527: CY62256LL
4Mbit CMOS Flash Memory Static RAM
CE
Control Program/Erase
Write State
OE
Input Logic High Voltage
Machine (WSM)
WE
Address State
Flash
Latch Register
A0~A17
Array Array A 10
and
Buffer Source A 9
A
HV 8
A
7
Command
Y-Pass A
6
Data Decoder
Gate A
5
8
A
4
A
3
A
2
Command
Sense PGM
Data Latch
CE
Amplifier Data HV
WE
OE
Program
Data Latch
Q0~Q15/A-1
I/O Buffer
9
C D E
RX-V2300/DSP-AX2300: Page 84
RX-V1300/RX-V1300RDS/HTR-5590/DSP-AX1300: Page 85
RX-V2300/DSP-AX2300: Page 86 H4
to FUNCTION
RX-V1300/RX-V1300RDS/HTR-5590/DSP-AX1300: Page 87 H4
to OPERATION (3)
2.7 4.9 REGULATOR
3.3 4.9
0 2.7 4.7 4.9
3.3 4.9
2.7
0
0 0
W502
0
DSP/DOLBY/DTS
2.7
0.5
0
3.9
Point 1 Pin 1 of IC514
0
0.2
0.2
3.5
0.2
4.8
12
11 2.7
4.8 2.7
13 4.9
4.9
4.8
0.1 9
0.1
8
0.1
10 3.9
0
3.9
1
3.9
0
2.7
0.1
0.2
1.4
2.8
1.8
2.8 0.2
1.8
2.8 0.1
1.8
3.4
3.5
2.6
0
~ 3.5
0.1
2.7 0
0.1
PLD
0.3
2.7
0 3.5
~
0.1 3.4
2.7 3.4
2.7 3.4
3.5 3.5
0.1 3.5
0.1 3.5
0.1
3.4
1.4
4.9 3.4
0.2 3.4
4.9 0
4.8 3.4
3.4
0.1
3.5 0
0
4.8
0 3.5
IC526: XC9572XL-10TQ100C
CPLD
3
JTAG
JTAG Port In-System Programming Controller
1
Controller
I/O
I/O
I/O 0
INPUT
I/O
BUFFER
I/O 1
I/O I/O
2
I/O
512x512 3
ARRAY
I/O 4
I/O
5
I/O
I/O I/O
POWER 6
Blocks
DOWN I/O
I/O 7
COLUMN
DECODER
I/O
I/O
3
I/O/GCK
1
I/O/GSR
2
I/O/GTS
F G
C1
C1 RX-V2300/DSP-AX2300: Page 84 D1
RX-V1300/RX-V1300RDS/HTR-5590/DSP-AX1300: Page 85 D1
to FUNCTION
MAIN L (ANALOG IN)
A/D CONVERTER
0 0
0
4.9 3.4
0 2.5
0 2.5
4.9
1.8 2.5
1.8 2.5
3.0
1.8
0.2 4.9
0.2
0.2
2.7
0
0.2
3.5
3.5
0.1
3.4
D/A CONVERTER
3.5
3.4
3.4
3.3
3.5
3.3
3.5 2.3
3.3
2.3
1.4
3.3
1.8 5.0
3.5
1.8 0
0.8
1.8 2.3
0.9
0.1 2.3
0.1
0
0.1
0 2.3
0
0 4.9
1.8
1.8
1.8
0.2
0.1
0.1
0.2
2.7
0
0.1
2.5
0.1
2.5
D/A CONVERTER
2.5
3.4 2.5
0 4.9
1.8 0
1.8 2.5
0.8 2.5
1.8 2.5
0 2.5
0.9 2.5
2.5
0
DECODER
1.8
1.8
0
2.6
0.1
2.8
2.7
2.7
3.5
4.9 4.8
4.8
2.7
4.9
0
IC524: CS5360-KSR IC517: PQ025EZ5MZP
Stereo A/D Converter Regulator
VA+ VD+ RSY MCLK OVFL FRAME SCLK LRCK
3 6 18 7 2 10 8 12 Vin 1
SDATA
9
CMOUT 15 Voltage Reference 20 DIF0
Serial Output Interface
54 Function
19 DIF1
Block 1
18
Macrocells AINL- 16 + +
LP Filter +
1 to 18 AINL+ – Digital Decimation High Pass
17
S/H – – Filter Filter
Comparator
DAC
54 AINR- + +
Function 14
LP Filter +
Block 1 AINR+ 13 – Digital Decimation High Pass
–
18 S/H – Filter Filter
Macrocells
Comparator
1 to 18
DAC
4 5 11 1
AGND DGND PU HP DEFEAT
54 Function
Block 1
18
Macrocells
1 to 18
# All voltages are measured with a 10MΩ/V DC electric volt meter.
54
Function # Components having special characteristics are marked s and must be
Block 1
18
Macrocells replaced with parts having specifications equal to those originally
1 to 18
installed.
# Schematic diagram is subject to change without notice.
H I
RX-V2300/DSP-AX2300/RX-V1300/RX-V1300RDS/HTR-5590/DSP-AX1300
IC501, 502: TC74HCU04AF IC503: TC74HCT00AF IC508: CS4392-KZR
Hex Inverters Quad 2-Input Nand Gate 2-Channel D/A Converter
1A 1 14 Vcc
1A 1 14 VCC
1B 2 13 4B
1Y 2 13 6A
1Y 3 12 4A
2A 4 11 4Y
2A 3 12 6Y
2B 5 10 3B
2Y 4 11 5A
2Y 6 9 3A
3A 5 5Y
10 GND 7 8 3Y
3Y 6 9 4A
GND 7 8 4Y LRCK
SDATA
4.9
4.9
4.9 4.9 IC510 : CS4382-KQR
8-Channel D/A Converter
2.5
11.7 11.7
2.5
2.5 0 2.5 2.5
2.5 2.5
2.5 2.5
2.5 2.5
2.5 2.5
2.5 2.5
0 0
2.5 2.5 2.5
-11.7
2.5 -11.7
RST
19
0
0
VLS 43
SCLK1 9
LRCK1 7
SCLK2 12
LRCK2 10
SDIN1 8
13K
0
11.7
0 SDIN2 11
0
SDIN3 13
0
0 13K
-11.1 SDIN4
0 14
-11.1
0
0 0
0
0
-11.1
13K
0
0
0.4
0
13K -11.7 MCLK 6
CENTER
8
DSDxx
0 11.7
0
1.3
0 0
-11.7
-11.1
0
0
-11.1 IC509, 518~523: NJM2068MD
0
0 Dual OP-Amp.
0
OUT 1
1
0
0
1.3 –IN 1 2
+IN 1 3
–V 4
CC
11.7
1.9
2.9
0
1.9 0.6 0
IC512: TC74HCT08AF
Quad 2-Input And Gate
0
0
0
0 0 -11.1 0
1A 1
1B 2
0 0 0
1.9
-11.1
1Y 3
0
1.9
-11.7
2A 4
2B 5
FRONT L
2Y 6
0 GND 7
6.8K 11.7
1.9
3.3 2.9 2.9
0
1.9 0.6 0
6.8K
0
2.9 IC515: MSM514260E-60JS
0
0
4Mbit DRAM
0
0 2.9 0
0.6
6.8K
3.3 0
RAS
1.9
2.9
2.9
0
6.8K 1.9
-11.7
LCAS
UCAS
REAR L
11.7
3.3 1.9
2.9 2.9
0
0
0.6
2.9 1.9
0
2.9 A0~A8
0 0
0
2.9
0 0
0
0.6
2.9
0
0
3.3
2.9 1.9
2.9 0
1.9
-11.7
VCC
VSS
IC525: CS493292-CLR
Audio Decoder
36 8 9 10 11 14 15 16 17 18 5 4 19 7 6 20 21
3 Vo
Parallel or Serial Host Interface
CMPDAT, SDATAN2, RCV958 27
Compressed
CMPCLK, SCLKN2 Data Input
28
Interface Frame
2 Vc
CMPREQ, LRCLKN2 29 Shifter 24-Bit
5
DSP Processing
GND Input
RAM RAM
Buffer
Program Data RAM Output
SCLKN1, STCCLK2 25
Digital Controller Output
Memory Memory Buffer
Audio
Formatter
LRCLKN1 26
Input RAM RAM
Interface Program Data
SDATAN1
22
Memory Memory
RAM Input
Buffer
STC
CLKIN 30
PLL
CLKSEL Clock Manager
31
32 33 34 35 24 13 2 23 12 1
x: NOT USED
O: USED / APPLICABLE
J K L
9 7 8 10 20 13 12 11
MODE SELECT EXTERNAL
RST 1
REFERENCE
(CONTROL PORT) MUTE CONTROL
∆∑ AOUTA+
VOLUME INTERPOLATION ANALOG 18
CONTROL FILTER DAC FILTER 19 AOUTA-
SCLK
4
SERIAL MIXER
5
PORT
3
∆∑ 15 AOUTB+
VOLUME INTERPOLATION ANALOG
CONTROL FILTER DAC FILTER 14 AOUTB-
6
42 15 16 17 18 41 22
Control Port (Stand-Alone Mode Select) External Mute Control
39 AOUTA1+
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
40 AOUTA1-
Mixer
38 AOUTB1+
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
AOUTB1-
37
35 AOUTA2+
Volume Control Interpolation Filter ∆∑ DAC Analog Filter
36 AOUTA2-
Mixer
34 AOUTB2+
Volume Control Interpolation Filter ∆∑ DAC Analog Filter
33 AOUTB2-
29 AOUTA3+
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
30 AOUTA3-
Mixer
28 AOUTB3+
Volume Control Interpolation Filter ∆∑ DAC Analog Filter
27 AOUTB3-
AOUTA4+
25
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
AOUTA4-
26
Mixer
+2 AOUTB4+
24
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
23 AOUTB4-
21 VQ
FILT+
20
4 5 31 32
IC513: NJM2904M
8 +V Dual OP-Amp
CC
V–
7 OUT 2
+ – + –
6 –IN 2
5 +IN
2
Q6
Q2 Q3 Q5
– Q1 Q4
Q7
INPUTS
OUTPUT
14 Vcc
Q13
+
13 4B
Q11
Q12
12 4A
Q10
11 4Y
Q8 Q9
10 3B
9 3A
8 3Y
WE OE
13 27
Timing
14
Generator
I/O
Controller
29
Output
28 8 8
I/O
Buffers
Controller
DQ1~DQ8
Column
Input
9 Address 9 Column Decoders
8 8
Buffers Buffers
I/O
Internal Sense Amplifiers
Refresh 16 16
Selector
Addess
Control Clock
Counter
Input
8
8
Buffers
Row
Row
9 Address 9
Word Memory DQ9~DQ16
Deco-
Buffers Drivers Cells
ders
Output
8
8
Buffers
20
On Chip
VBB Generater
21
IC516: µPC29M33T-E1
Voltage Regulator
1 INPUT
Safety Drive
37 DD
Limiter
38 DC
Amp.
3 OUTPUT
MCLK
44
43 SCLK
42 LRCLK
AUDATA2
39
40 AUDATA1
41 AUDATA0
Excessive Electric
AUDATA3, XMT958
3
Current Protection
2 GND
83