Denon S-301 Service Manual page 17

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ES6138F Pin Description
Name
VEE 1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
2:7, 10:16, 19:23,
LA[21:0]
VSS 8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
9, 35, 44, 83, 121,
VCC
RESET#
TDMDX
RSEL
TDMDR
TE
L 13942296513
TDMCLK
TDMFS
TDMTSC#
TWS
SEL_PLL2
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Pin Numbers I/O Definition
P I/O power supply.
183, 193, 201
O RISC port address bus.
204:207
G Ground.
200, 208
P Core power supply.
139, 172
24 I Reset input (active-low).
O TDM transmit data output.
I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ
resistor; read only during reset.
25
28 I TDM receive data input.
29 I TDM clock input.
30 I TDM frame sync input.
31 O TDM output enable (active-low).
O Audio transmit frame sync output.
I System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-kΩ resistor; read
only during reset.
32
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8
RSEL Selection
0 16-bit ROM
1 8-bit ROM
Q Q
3 6 7 1 3
SEL_PLL2 SEL_PLL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
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2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
SEL_PLL0 PLL Settings
0 DCLK × 4.5
1 DCLK × 5.0
0 Bypass
1 DCLK × 4.0
0 DCLK × 4.25
1 DCLK × 4.75
0 DCLK × 5.5
1 DCLK × 6.0
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S-301
9 9
2 8 9 9