Block Diagram - Harman Kardon AVR247 Service Manual

harman/kardon

3. Block Diagram

CS
SCK
INTERFACE
CONTROL
SI
SO
WP
4. Memory Array
3600A–DFLASH–11/05
Figure 2-1. 8-SOIC Top View
CS 1
SO 2
WP 3
GND 4
CONTROL AND
PROTECTION LOGIC
AND
LOGIC
To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions. The Figure 4-1 on page 4
breakdown of each physical sector.
AT26DF081A [Preliminary]
8 VCC
7 HOLD
6 SCK
5 SI
Y-DECODER
X-DECODER
illustrates the breakdown of each erase level as well as the
AVR247/230 Service Manual
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
Y-GATING
FLASH
MEMORY
ARRAY
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