Sony TA-E9000ES Service Manual page 61

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Pin No. Pin Name
50 TSTD
51 VSS8
52 VDD5
53 ED16
54 ED17
55 ED18
56 ED19
57 ED20
58 ED21
59 ED22
60 ED23
61 VSS9
62 ED24
63 ED25
64 ED26
65 ED27
66 ED28
67 ED29
68 ED30
69 ED31
70 XOE
71 VSS10
72 VDD6
TE
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73 CAS
74 XWE
75 RAS
76 EA0
77 EA1
78 EA2
79 EA3
80 EA4
81 VSS11
82 VDD7
83 EA5
84 EA6
85 EA7
86 EA8
87 EA9
88 EA10
89 EA11
90 EA12
91 VSS0
92 EA13
93 EA14
www
94 EA15
95 EA16
96 TSTA
.
97 PLDIVF
98 PLDIVB
99 CLKI
100 CLKO
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I/O
I Test data input "L" = normal "H" = test
— Ground
— Power supply (+3.3V)
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
— Ground
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
O External RAM output enable
— Ground
— Power supply (+3.3V)
O External RAM column address strobe
O External RAM write enable
O External RAM raw adress storobe
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
— Ground
— Power supply (+3.3V)
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
I/O External RAM address output/test data input
O External RAM address output
— Ground
O External RAM address output
O External RAM address output
O External RAM address output
O External RAM address output
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I Test data input "L" = normal "H" = test
i
I PLL input frequency setup "L" = 256Fs "H" = 128Fs
I PLL output frequency setup "L" = 768Fs "H" = 1024Fs
I Master clock input
O Master clock output
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Function
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