Skyworth 42E68 Instruction Manual page 41

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PIN
NAME NO.
NC 8
OC_ADJ 7
OSC_RES 16
OUT_A 1
OUT_B 46
OUT_C 39
OUT_D 36
PDN 19
PGND_AB 47, 48
PGND_CD 37, 38
PLL_FLTM 10
PLL_FLTP 11
PVDD_A 2, 3
PVDD_B 44, 45
PVDD_C 40, 41
PVDD_D 34, 35
RESET 25
SCL 24
SCLK 21
SDA 23
SDIN 22
SSTIMER 6
STEST 26
FAULT 14
VR_ANA 12
VR_DIG 18
VREG 31
Copyright © 2008–2009, Texas Instruments Incorporated
PIN FUNCTIONS (continued)
TYPE 5-V TERMINATION
(1)
TOLERANT
–
AO
AO
O
O
O
O
DI 5-V
P
P
AO
AO
P
P
P
P
DI 5-V
DI 5-V
DI 5-V Pulldown
DIO 5-V
DI 5-V Pulldown
AI
DI
DO
P
P
P
Product Folder Link(s):
(2)
No connection
Analog overcurrent programming. Requires resistor to ground.
Oscillator trim resistor. Connect an 18.2-k
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Pullup Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating PWM stop
sequence.
Power ground for half-bridges A and B
Power ground for half-bridges C and D
PLL negative loop filter terminal
PLL positive loop filter terminal
Power supply input for half-bridge output A
Power supply input for half-bridge output B
Power supply input for half-bridge output C
Power supply input for half-bridge output D
Pullup Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
2
I C serial control clock input
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
2
I C serial control data interface input/output
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
Controls ramp time of OUT_X to minimize pop. Leave this pin floating
for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The
capacitor determines the ramp time.
Factory test pin. Connect directly to DVSS.
Backend error indicator. Asserted LOW for over temperature, over
current, over voltage, and under voltage error conditions. De-asserted
upon recovery from error condition.
Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
Digital regulator output. Not to be used for powering external circuitry.
TAS5707
SLOS556A – NOVEMBER 2008 – REVISED APRIL 2009
DESCRIPTION
1% resistor to DVSSO.
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TAS5707
7