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Pin Function
N
. o
P
n i
N
a
m
e
/ I
O
S
u
b
Q
8
1
S
Q
S
O
O
C
D
T
E
X
2
S
Q
C
K
I
C
o l
k c
n i
3
X
R
S
T
I
S
s y
e t
m
4
S
Y
S
M
I
M
u
e t
n i
5
D
A
T
A
I
S
r e
l a i
d
L
a
c t
h
n i
6
X
L
A
T
I
S
r e
l a i
d
7
C
L
O
K
I
S
r e
l a i
d
8
S
E
N
S
O
S
E
N
S
o
9
S
C
L
K
I
C
o l
k c
n i
−
1
0
V
D
g i
t i
l a
D
D
1
1
A
T
S
K
/ I
O
n I
p
t u
a
1
2
S
P
O
A
I
M
c i
o r
c
o
1
3
S
P
O
B
I
M
c i
o r
c
o
1
4
X
L
O
N
O
M
c i
o r
c
o
1
5
W
F
C
K
O
W
F
C
K
X
U
G
F
1
6
X
U
G
F
O
s
w
c t i
h
n i
X
P
L
C
K
1
7
X
P
C
K
O
c
o
m
m
a
G
F
S
o
u
1
8
G
F
S
O
s
w
c t i
h
n i
C
2
P
O
o
1
9
C
2
P
O
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c
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m
m
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p t
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2
0
S
C
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c
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2
1
C
O
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T
/ I
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n I
p
t u
a
2
2
M
R I
R
/ I
O
M
r r i
r o
s
2
3
D
F
C
T
/ I
O
D
e
e f
t c
2
4
F
O
K
/ I
O
F
o
c
u
s
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s i
2
5
L
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K
/ I
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o
u
p t
u
s t
s
a
m
p
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2
6
M
D
P
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v r
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c
2
7
S
S
T
P
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t c
o i
2
8
S
F
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d
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2
9
S
R
D
R
O
3
0
T
F
D
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T
a r
k c
n i
3
1
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R
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3
2
F
F
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c
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r d
3
3
F
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R
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−
3
4
V
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g i
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l a
S
S
3
5
T
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T
p
3
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T
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1 :
6
9 .
3
8
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C
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t n
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3
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4
0
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r r
Notes)
• PCMD is an MSB first. two's complement output.
• GTOP is used to monitor the frame sync protection status. (High:sync protection window released)
• XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs.
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
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45
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