CONTENTS SAFETY PRECAUTIONS PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY SENSITIVE(ES)DEVICES CONTROL BUTTON LOCATIONS AND EXPLANATIONS PREVERTION OF STATIC ELECTRICITY DISCHARGE ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST BRACKET EXPLOSED VIEW AND PART LIST MISCELLANEOUS ELECTRICAL CONFIRMATION VI DEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION...
1. SAFETY PREAUTIONS 1.1 GENERAL GUIDELINES 1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have been overheated or damaged by the short circuit. 2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers shields are properly installed.
4.PREVENTION OF STATIC ELECTRICITY DISCHARGE The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human body. Use due caution to electrostatic breakdown when servicing and handling the laser diode. 4.1.Grounding for electrostatic breakdown prevention Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged by static electricity in the working environment.Proceed servicing works under the working environment where grounding works is completed.
5.3 MISCELLANEOUS 5.3.1 Protection of the LD(Laser diode) Short the parts of LD circuit pattern by soldering. 5.3.2 Cautions on assembly and adjustment Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are grounded,and that personnel wear wrist straps for ground. Open the LD short lands quickly with a soldering iron after a circuit is connected.
6.Electrical Confirmation 6.1. Video Output (Luminance Signal) Confirmation DO this confirmation after replacing a P.C.B. Measurement point Mode Disc Color bar 75% DVDT-S15 Video output terminal PLAY(Title 46):DVDT-S15 PLAY(Title 12):DVDT-S01 DVDT-S01 Measuring equipment,tools Confirmation value 200mV/dir,10 sec/dir 1000mVp-p±30mV Purpose:To maintain video signal output compatibility. 1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
6.2 Video Output(Chrominance Signal) Confirmation Do the confirmation after replacing P.C.B. Measurement point Mode Disc Color bar 75% DVDT-S15 Video output terminal PLAY(Title 46):DVDT-S15 PLAY(Title 12):DVDT-S01 DVDT-S01 Measuring equipment,tools Confirmation value Screwdriver,Oscilloscope 200mV/dir,10 sec/dir 621mVp-p±30mV Purpose:To maintain video signal output compatibility. 1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
FLI2300 Digital Video Converter Data Sheet DESCRIPTION Front End Processing • Motion Adaptive Noise Reduction - Improves The FLI2300 is a highly integrated digital video picture quality for off-air material. format converter for CRT-TV applications using patented deinterlacing and post processing algorithms •...
FLI2300 Digital Video Converter Data Sheet BLOCK DIAGRAMS Figure 2.1: FLI2300– Simplified Internal Block Diagram Port 2 16/20/24-bit 8-bit Noise Reducer, Output RBG/YCrCb Input Processor Vertical and 656 Input Deinterlacer, Frame Processor with Digital Outputs with Auto Sync Horizontal Rate Converter and Sync Generation and auto Adjust Scalers...
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FLI2300 Digital Video Converter Data Sheet PIN INFORMATION Pin Diagram Figure 3.1: Pinout Information HSYNC1_PORT1 1 5 5 VSYNC1_PORT1 G/Y/Y_OUT_7 FIELD ID1_PORT1 G/Y/Y_OUT_6 IN_CLK1_PORT1 G/Y/Y_OUT_5 HSYNC2_PORT1 G/Y/Y_OUT_4 VSYNC2_PORT1 G/Y/Y_OUT_3 FIELD ID2_PORT1 1 5 0 G/Y/Y_OUT_2 VDD1 G/Y/Y_OUT_1 G/Y/Y_OUT_0 IN_CLK2_PORT1 B/Cb/D1_0 VDD8 B/Cb/D1_1 1 4 5...
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FLI2300 Digital Video Converter Data Sheet Pin details Table 3.1: FLI2300 pin details Internal Voltage Pin Name I/O Type Drive Pull up/ Description Tolerance Pulldown Horizontal sync or reference -CTL1 of Port 1 HSYNC1_PORT1 Input Vertical sync or reference -CTL1 of Port 1 VSYNC1_PORT1 Input FIELD ID1_PORT1...
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FLI2300 Digital Video Converter Data Sheet Internal Voltage Pin Name I/O Type Drive Pull up/ Description Tolerance Pulldown 44 DEV_ADDR0 Device address setting 0 Input 45 SCLK 8 mA 2-wire serial control bus clock 46 SDATA 8 mA 2-wire serial control bus data 47 RESET_N Input Reset...
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FLI2300 Digital Video Converter Data Sheet Internal Voltage Pin Name I/O Type Drive Pull up/ Description Tolerance Pulldown 89 VSS Ground Ground 90 TEST IN Test input-Connect to ground Input 91 SDRAM ADDR(10) 8 mA SDRAM address bus * Tristate O/P 92 SDRAM ADDR(9) 8 mA SDRAM address bus *...
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FLI2300 Digital Video Converter Data Sheet Internal Voltage Pin Name I/O Type Drive Pull up/ Description Tolerance Pulldown 130 B/U/Pb_OUT_2 8 mA Digital video output – Blue/U/Pb Tristate O/P 131 B/U/Pb_OUT_3 8 mA Digital video output – Blue/U/Pb Tristate O/P 132 B/U/Pb_OUT_4 8 mA Digital video output –...
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FLI2300 Digital Video Converter Data Sheet Internal Voltage Pin Name I/O Type Drive Pull up/ Description Tolerance Pulldown 175 DAC_AVSSG Analog Ground for G channel Ground 176 DAC_ROUT Output 34 mA Analog R/V output 177 DAC_AVDDR Power 3.3 V – Analog power pin for R channel 178 DAC_AVSSR Ground Analog Ground for R channel...
8. Am29LV160D 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation Embedded Algorithms — Full voltage range: 2.7 to 3.6 volt read and write — Embedded Erase algorithm automatically operations for battery-powered applications preprograms and erases the entire chip or any combination of designated sectors...
PRODUCT SELECTOR GUIDE Family Part Number Am29LV160D Speed Option Voltage Range: V = 2.7–3.6 V -120 Max access time, ns (t Max CE# access time, ns (t Max OE# access time, ns (t Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM –...
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CONNECTION DIAGRAMS RESET# BYTE# DQ15/A-1 DQ14 DQ13 DQ10 DQ12 DQ11 FBGA Top View, Balls Facing Down BYTE# DQ15/A-1 DQ14 DQ13 RESET# DQ12 RY/BY# DQ10 DQ11 Special Handling Instructions Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. Special handling is required for Flash Memory products The package and/or data integrity may be compromised in FBGA packages.
HY57V641620HG 4 Banks x 1M x 16Bit Synchronous DRAM 8.1 HY57V641620HG DESCRIPTION The Hyundai HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16. HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock.
HY57V641620HG PIN CONFIGURATION DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 54pin TSOP II 400mil x 875mil 0.8mm pin pitch LDQM UDQM /CAS /RAS A10/AP PIN DESCRIPTION PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the Clock rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one...
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HY57V641620HG FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 16 I/O Synchronous DRAM Self refresh logic Internal Row & timer counter 1Mx16 Bank 3 1Mx16 Bank 2 Row active Decoders 1Mx16 Bank 1 1Mx16 Bank 0 Memory refresh Cell Array Column Column Active UDQM...
SiI 164 PanelLink PanelLink PanelLink PanelLink Transmitter September 2002 Data Sheet General Description Features • Scaleable Bandwidth: 25 - 165MHz Flexible The SiI 164 transmitter uses PanelLink ® Digital • Graphics Controller Interface: 12-bit or 24-bit technology to support displays ranging from VGA to mode 1 pixel/clock inputs UXGA resolutions (25 - 165Mpps) in a single link •...
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SiI 164 PanelLink Transmitter Data Sheet Functional Description The SiI 164 is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 24 bits for data Input to allow for panel support up to UXGA resolution. Figure 2 shows the functional blocks of the chip. PanelLink PanelLink PanelLink...
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SiI 164 PanelLink Transmitter Data Sheet Data Capture Logic Video data is input to the SiI 164 by way of a 12-bit or 24-bit interface. The functionality of this interface is affected by several of the configuration register settings, as follows. •...
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SiI 164 PanelLink Transmitter Data Sheet Electrical Specifications Absolute Maximum Conditions Absolute Maximum Conditions are defined as the worst case conditions the part will tolerate without sustaining damage. Permanent device damage may occur if absolute maximum conditions are exceeded. Proper operation under these conditions is not guaranteed.
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SiI 164 PanelLink Transmitter Data Sheet DC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions Units Differential Voltage Single ended = 50Ω, R = 510Ω LOAD EXT_SWING peak to peak amplitude Differential High-level Output AVCC Voltage µA Differential Output Short Circuit = 0 V Current...
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SiI 164 PanelLink Transmitter Data Sheet AC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions Units Figure IDCK Period, 1-pixel/clock Figure 3 IDCK Frequency, 1-pixel/clock IDCK High Time at 165MHz Figure 3 IDCK Low Time at 165MHz Figure 3 Worst Case IDCK Clock Jitter IJIT...
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SiI 164 PanelLink Transmitter Data Sheet Input Timing Diagrams 2.0 V 2.0 V 2.0 V 0.8 V 0.8 V Figure 3. Clock Cycle High/Low Times 80% V 20% V Figure 4. Low Swing Differential Times ISEL/RST# RESET Figure 5. ISEL/RST# Minimum Timing...
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SiI 164 PanelLink Transmitter Data Sheet 50 % 50 % IDCK SIDF HIDF D[23:0], DE, 50 % 50 % HSYNC,VSYNC SIDR HIDR Figure 6. Input Data Setup/Hold Time to IDCK 0.8 V 0.8 V VSYNC, HSYNC, VSYNC, HSYNC, 0.8 V 0.8 V CTL[3:1] CTL[3:1]...
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SiI 164 PanelLink Transmitter Data Sheet Pin Descriptions Input Pins Pin Name Pin # Type Description Top half of 24-bit pixel bus. D[23:12] 36-47 When BSEL = HIGH, this bus inputs the top half of the 24-bit pixel bus. When BSEL = LOW, these bits are not used to input pixel data.
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SiI 164 PanelLink Transmitter Data Sheet Pin Descriptions (cont’d) Configuration Pins Pin Name Pin # Type Description Monitor Sense. This pin is an open collector output. The behavior of this output depends on MSEN whether I C interface active: C bus inactive (ISEL/RST# = LOW) HIGH level indicates a powered on receiver is detected at the differential outputs.
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SiI 164 PanelLink Transmitter Data Sheet Pin Descriptions (cont’d) Input Voltage Reference Pin Pin Name Pin # Type Description VREF Analog In Input Reference Voltage. Selects the Swing range of the digital inputs, which include only D[23:0], IDCK+, IDCK-, DE, VSYNC, and HSYNC. Input pins SCL and SDA, RST, BSEL, DSEL, EDGE and PD# require 3.3V high swing signals and are not changed by the VREF input.
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SiI 164 PanelLink Transmitter Data Sheet C Registers C Register Mapping Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 VND_IDL (RO) 0x01 VND_IDH (RO) 0x02 DEV_IDL (RO) 0x03 DEV_IDH (RO) 0x04 DEV_REV (RO) 0x05...
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SiI 164 PanelLink Transmitter Data Sheet C Register Definitions Register Name Access Description VND_IDL Vendor ID Low byte (01h) VND_IDH Vendor ID High byte (00h) DEV_IDL Device ID Low byte (06h) DEV_IDH Device ID High byte (00h) DEV_REV Device Revision (00h) FRQ_LOW Low frequency limit at 1-pixel/clock mode (MHz) (19h) FRQ_HIGH...
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SiI 164 PanelLink Transmitter Data Sheet C Register Definitions (cont’d) Register Name Access Description CFG[7:0] Contains state of inputs D[23:16]. These pins can be used to provide user selectable configuration data through the I C bus. Only available in 12-bit mode PFEN PLL Filter Enable in the VDJK Register.
8.2 MT1389 MT1389 Progressive-Scan DVD Player SOC Specifications are subject to change without notice MediaTek MT1389 is a DVD player system-on-chip (SOC) which incorporates advanced features like high quality TV encoder and state-of-art de-interlace processing. The MT1389 enables consumer electronics manufacturers to build high quality, cost-effective DVD players, portable DVD players or any other home entertainment audio/video devices.
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MT1389 PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE General Feature List 1024-bytes on-chip RAM Super Integration DVD player single chip Up to 4M bytes FLASH-programming interface High performance analog RF amplifier Supports 5/3.3-Volt. FLASH interface Servo controller and data channel processing Supports power-down mode MPEG-1/MPEG-2/JPEG video Supports additional serial port...
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MT1389 PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE Audio Effect Processing TV Encoder Dolby Digital (AC-3)/EX decoding Six 108MHz/12bit DACs DTS/DTS-ES decoding Support NTSC, PAL-BDGHINM, PAL-60 MLP decoding for DVD-Audio Support 525p, 625p progressive TV format MPEG-1 layer 1/layer 2 audio decoding Automatically turn off unconnected channels MPEG-2 layer1/layer2 2-channel audio Support PC monitor (VGA)
10. SPARE PARTS LIST DV985S MATERIAL LIST 1. POWER BOARD MATERIAL SPECIFICATIONS/PART NUMBER QUANTITY LOCATION CARBON FILM RESISTOR 1/4W1.5K±5%SHAPED10 R516 CARBON FILM RESISTOR 1/4W100Ω±5% R521 CARBON FILM RESISTOR 1/4W330Ω±5%SHAPED10 R506 CARBON FILM RESISTOR 1/4W1K±5%SHAPED10 R507,R513 METAL FILM RESISTOR 1/4W2.7K±1%SHAPED10 R509 METAL FILM RESISTOR 1/4W10K±1%...