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5
Table 3 : PCR
QQ
3 7 63 1515 0
Pin name
PWMOUT
Table 4 : JTAG
Pin name
JTDI
JTCK
JTDO
JTMS
JTRST
EDINT
A : In normal use, pin 144 is exclusive to the NMI input. In debugging mode, pin144 is the EDINT input.
Table 5 : Test
Pin name
TEST
Table 6 : Unified Memory Interface
Pin name
TE
L 13942296513
DADD0~DADD12 190 (DADD0), 189, 188, 187, 183, 182, 181, 180,
DQ0~DQ15
DCSB
DRASB
DCASB
DWEB
DQM0~DQM1
DBA0~1
DCKE
DQS1
DCLK
Table 7 : Audio Output
Pin name
AMCK
ALRCK
ABCK
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ATX
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Pin no.
141
PWM output to control the 27MHz VCXO
Pin no.
147
EJTAG data input
150
EJTAG clock
148
EJTAG data output
149
EJTAG mode select
151
EJTAG reset
A
144
Debug interrupt
Pin no.
75
For test use only. Connect to GND.
Pin nos.
179, 178, 191, 174, 173 (DADD12)
212 (DQ0), 211, 210, 209, 208, 204, 203, 202, 166,
165, 159, 158, 157, 156, 155, 154 (DQ15)
196
197
198
199
200, 169
193, 192
172
167
171
Pin no.
66
PCM Audio Master Clock
73
PCM Audio L/R Clock
70
PCM Audio Data Clock
72
PCM Audio Data – L/R
71
SPDIF Digital audio output
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2 9
8
Description
Description
Description
Q Q
3
6 7
1 3
1 5
Address Bus
Data Bus
Chip select
RAS signal
CAS signal
Command write enable
Data mask
Bank address
Clock enable
Connect to DCLK
Clock output
Description
co
.
DVR-540HX-S
7
8
9 4
2 8
In/Out
O
In/Out
I
I
O
I
I
I
In/Out
I
Description
In/Out
0 5
8
2 9
9 4
2 8
O
I/O
O
O
O
O
O
O
O
I
O
In/Out
O
O
O
m
O
O
9 9
A
B
C
9 9
D
E
F
143
8
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