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1
UPD6110GM-100UEVA (DTBR ASSY : IC106)
QQ
3 7 63 1515 0
• DTB Receiver/Decoder
Block Diagram
A
JTAG/N-Wire
B
Stream input
IEEE 1394
link
C
Pin Function
TE
L 13942296513
Table 1 : Power and Ground
Pin name
GND
11, 12, 28, 42, 43, 54, 67, 68, 110, 138, 139, 152, 161,
162, 163, 164, 176, 184, 185, 194, 206, 214, 215
DGND
84, 94, 95
D
AGND
77, 80, 87, 90
PAGND
135
DVDD
85, 96
VDD1
13, 44, 69, 134, 177, 207
VDD2
153, 160, 175, 186, 195, 205, 213
VDD3
27, 53, 109, 140, 216
AVDD
78, 81, 88, 91
PAVDD
136
E
Table 2 : System
Pin name
Pin no.
CLK27IN
RSTOUT
www
RSTSWB
NMI
F
142
1
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2
ROM
Main
Sub-
I/F
CPU
CPU
Host I/F
Command Bus
TS-DEMUX
DMA
with optional
Controller
descrambling
Memory Bus
Unified Memory Controller
Pin nos.
137
27MHz Input clock from VCXO
142
RESET out from Watch Dog Timer
143
Hardware RESET
x
ao
y
144
Non Maskable Interrupt (see note A in table8 below)
.
i
DVR-540HX-S
2
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3
8
GIO
Timers
I/F
Audio
Controller
MPEG
Graphics
Video
& Display
Decoder
SDRAM
Q Q
3
6 7
1 3
Main supply ground
Digital Ground for video DACs
Analog Ground for Video DACs
Ground for PLL 1.5V supply
Digital VDD (1.5V) for video DACs
1.5V supply (core)
3.3V for Unified Memory I/F IO buffers
3.3V for IO buffers
3.3V supply for Video DACs
1.5V supply for PLL
Description
u163
.
3
4
2 9
9 4
2 8
Peripherals
Interfaces
SPDIF
PCM (L+R)
Digital
Video
Y/C
Encoder
CVBS
RGB
1 5
0 5
8
2 9
9 4
Description
In/Out
I
O
m
I
co
I
4
9 9
2 8
9 9
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