Harman Kardon AVR 230 Service Manual page 79

Harman Kardon
8 Mbit SPI Serial Flash
SST25VF080B
PIN DESCRIPTION
CE#
SO
WP#
V SS
FIGURE 1: P
TABLE 1: P D
IN
Symbol Pin Name
SCK Serial Clock
SI Serial Data Input
SO Serial Data Output
CE# Chip Enable
WP# Write Protect
HOLD# Hold
V Power Supply
DD
V Ground
SS
©2006 Silicon Storage Technology, Inc.
V DD
1 8
2 7 HOLD#
Top View
SCK
3 6
4 5 SI
1296 08-soic S2A P1.0
8- SOIC
LEAD
A
IN SSIGNMENTS
ESCRIPTION
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin.
See "Hardware End-of-Write Detection" on page 12 for details.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the
device.
To provide power supply voltage: 2.7-3.6V for SST25VF080B
CE#
1
SO
2
Top View
WP# 3
V SS 4
1296 08-wson QA P2.0
8-
CONTACT
3
AVR 165/230V Service Manual
Data Sheet
8 V DD
HOLD#
7
6 SCK
5 SI
WSON
T1.0 1296
S71296-01-000 1/06
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