Table of Contents
Advertisement
Pin No.
Pin Name
VDD
61
VSS
62
DLDRI
63
64
CSWI
SLSRI
65
FLFRI
66
TEST3
67
68
CLK512
VSS
69
XRST
70
VDD
71
72
SCLK
XCS
73
SI
74
SO
75
76
DEXRI
DMLI
77
DMRI
78
VSS
79
80
PHRI
81
BCKAI
82
DQM
DLI
83
84
DRI
DCI
85
DLFEI
86
DLSI
87
88
DRSI
VSS
89
90 to 95
D15 to D10
VDD
96
97, 98
D9, D8
GND
99
100
D0
I/O
-
Power supply terminal (+3.3V)
-
Ground terminal
I
Surround back audio data input from the DSP
I
Center and sub woofer audio data input from the DSP
I
Surround audio data input from the DSP
I
Front audio data input from the DSP
I
Input terminal for the test
I
Master clock signal input from the DSP
-
Ground terminal
I
Reset signal input terminal "L": reset
-
Power supply terminal (+3.3V)
I
Serial clock signal input from the main system controller
I
Chip select signal input from the main system controller
I
Serial data input from the main system controller
O
Serial data output to the main system controller
-
Not used
I
Data input terminal for L-ch down mix Not used
I
Data input terminal for R-ch down mix Not used
-
Ground terminal
I
Clock signal input terminal Not used
I
Bit clock signal (2.8224 MHz) input terminal Not used
-
Not used
I
Front L-ch data input terminal Not used
I
Front R-ch data input terminal Not used
I
Center data input terminal Not used
I
Sub woofer data input terminal Not used
I
Surround L-ch data input terminal Not used
I
Surround R-ch data input terminal Not used
-
Ground terminal
I/O
Two-way data bus with the SD-RAM
-
Power supply terminal (+3.3V)
I/O
Two-way data bus with the SD-RAM
-
Ground terminal
I/O
Two-way data bus with the SD-RAM
Description
STR-DA2100ES
67
Advertisement
Table of Contents
