Integra DTR-8.3 Service Manual page 64

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SUB-MICROPROCESSOR-CONNECTION DIAGRAM 1
1
F 1 1
F 1 2
N P 3
N P 4
1 G 5
2 G 6
3 G 7
4 G 8
5 G 9
6 G 1 0
7 G 1 1
8 G 1 2
2
9 G 1 3
1 0 G 1 4
1 1 G 1 5
1 2 G 1 6
1 3 G 1 7
1 4 G 1 8
1 5 G 1 9
1 6 G 2 0
N C 2 1
N C 2 2
N C 2 3
N C 2 4
N C 2 5
N C 2 6
P 1 2 7
P 2 2 8
P 3 2 9
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P 8 3 4
P 9 3 5
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P 1 1 3 7
P 1 2 3 8
P 1 3 3 9
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P 1 6 4 2
P 1 7 4 3
P 1 8 4 4
P 1 9 4 5
P 2 0 4 6
P 2 1 4 7
P 2 2 4 8
P 2 3 4 9
P 2 4 5 0
P 2 5 5 1
P 2 6 5 2
P 2 7 5 3
4
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P 2 9 5 5
P 3 0 5 6
P 3 1 5 7
P 3 2 5 8
P 3 3 5 9
P 3 4 6 0
P 3 5 6 1
N C 6 2
N P 6 3
N P 6 4
F 2 6 5
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P 5
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P 1 1
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P 1 2
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P 1 4
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P 1 5
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P 1 6
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P 1 7
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P 1 8
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P 3 5
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P 3 4
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SW3
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SW2
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SW1
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VSYNCOUT
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XTALOUT2
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XTALIN2
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HSYNCOUT
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XTALOUT1
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XTALIN1
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29
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P H O N O T A P E
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P H O N E S
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S Y N C
8 2
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CIRCUIT 8 5
FLRES
8 6
8 7
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R D S
8 9
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INITIALIZING N T S C
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K 2
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