Ic Pin Function Description - Sony HCD-EX5 Service Manual

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6-17. IC Pin Function Description

µPD703030BYGF-M02-3BA Master Controller (Main Board)
• IC701
Pin No. Pin Name
1 DISP_DATA
2 DISP_CLK
3 IIC DATA
4 DACLAT
5 IIC CLK
6 CD_ADJ
7 CXD-DATA
8 CXD-CLK
9 EVDD
10 EVSS
11 CXD-XLT
12 PWM1
13 LDON
14 SENSE
15 SUBQ
16 SOFT_CHEK_1
17 SQCLK
18 SOFT_CHECK_2
19 PWM2
20 PWM3
21 VPP
TE
L 13942296513
22 BDPWR
23 BDRST
24 HP_IN
25 HP_MUTING
26 SPK-RELAY
27 HP MUTE
28 DIG-AMP-SLEEP
29 GEQ-DATA
30 GEQ-CLK
31, 32 DIM0, DIM1
33 LINE-MUTING
34 RESET
35 XT1
36 XT2
37 REGC
38 X2
39 X1
40 VSS
41 VDD
42 CLKOUT
43 PLL-CLK
44 PLL-DI(STpUCOM)
45 PLL-DO(UCOMpST)
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46 PLL-CE
47 ST-MUTING
48 STEREO
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49 TUNED
50 RDS-DATA
51 AM
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I/O
O Data output to the LCD601
O Clock output to the LCD601
I/O IIC data input/output (fixed at "H")
O Latch signal output to the DAC (IC301)
I/O IIC clock input/output (fixed at "H")
I CD adjustment mode input (fixed at "H")
O Data output to the CXD3068Q (IC101)
O Clock output to the CXD3068Q (IC101)
— Power supply (+5V)
— Ground
O Latch signal output to the CXD3068Q (IC101)
O PWM1 signal output
O Laser power control signal output
I SENSE signal input from the CXD3068Q (IC101)
I SUBQ data input from the CXD3068Q (IC101)
O Check terminal (open)
O SUBQ clock output to the CXD3068Q (IC101)
O Check terminal (open)
O PWM2 signal output
O PWM3 signal output
— Internal connection/power for writing to the flash ROM
O BD power control signal output
O BD reset signal output
I Headphone detection signal input
O Not used (open)
O Speaker relay control signal output
O PC/TAPE/MD output muting signal output
O Sleep signal output to the digital power amplifier (IC101)
O Data output to the pre-amplifier (IC121)
O Clock output to the pre-amplifier (IC121)
O Back light control signal output
O Line muting signal output
I System reset signal input
I Sub clock input
O Sub clock output
— Capacitor terminal for stabilizing the regulator output
O Main clock output
I Main clock input
— Ground
— Power supply (+5V)
O Clock output terminal (open)
O Clock output for the PLL for the tuner
I Data input from the PLL for the tuner
O Data output to the PLL for the tuner
O Chip enable signal output the PLL for the tuner
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O Muting signal output for the tuner
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I Stereo detection signal input
i
I Tuner tuning signal input
I RDS data input
O AM signal output for the RDS noise reduction
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