Haier HL40BG Service Manual page 42

5
U22C U22C
BCM3551KPB5G BCM3551KPB5G
BGA676_35X35 BGA676_35X35
BCM_DDR_ADDR0
K3
DDR0_ADDR00
BCM_DDR_ADDR1
K2
DDR0_ADDR01
K5 BCM_DDR_ADDR2
DDR0_ADDR02
K6 BCM_DDR_ADDR3
DDR0_ADDR03
BCM_DDR_ADDR4
L3
DDR0_ADDR04
L2 BCM_DDR_ADDR5
DDR0_ADDR05
M2 BCM_DDR_ADDR6
DDR0_ADDR06
M1 BCM_DDR_ADDR7
DDR0_ADDR07
BCM_DDR_ADDR8
L4
DDR0_ADDR08
BCM_DDR_ADDR9
L5
DDR0_ADDR09
K4 BCM_DDR_ADDR10
DDR0_ADDR10
Place all these TPs near BCM3560,
L6 BCM_DDR_ADDR11
DDR0_ADDR11
M3 BCM_DDR_ADDR12
D inside socket border.
DDR0_ADDR12
BCM_DDR_BA0
J1
DDR0_BA0
J2 BCM_DDR_BA1
DDR0_BA1
R2 BCM_DDR_DQ0
DDR0_DATA00
R3 BCM_DDR_DQ1
DDR0_DATA01
P6 BCM_DDR_DQ2
DDR0_DATA02
T1 BCM_DDR_DQ3
DDR0_DATA03
R4 BCM_DDR_DQ4
DDR0_DATA04
BCM_DDR_DQ5
T2
DDR0_DATA05
T3 BCM_DDR_DQ6
DDR0_DATA06
R5 BCM_DDR_DQ7
DDR0_DATA07
N3 BCM_DDR_DQ8
DDR0_DATA08
BCM_DDR_DQ9
M5
DDR0_DATA09
BCM_DDR_DQ10
P1
DDR0_DATA10
M6 BCM_DDR_DQ11
DDR0_DATA11
P2 BCM_DDR_DQ12
DDR0_DATA12
N4 BCM_DDR_DQ13
DDR0_DATA13
BCM_DDR_DQ14
P3
DDR0_DATA14
R1 BCM_DDR_DQ15
DDR0_DATA15
F2 BCM_DDR_DQ16
DDR0_DATA16
F1 BCM_DDR_DQ17
DDR0_DATA17
BCM_DDR_DQ18
H3
DDR0_DATA18
G3 BCM_DDR_DQ19
DDR0_DATA19
J6 BCM_DDR_DQ20
DDR0_DATA20
G2 BCM_DDR_DQ21
DDR0_DATA21
BCM_DDR_DQ22
J5
DDR0_DATA22
BCM_DDR_DQ23
G1
DDR0_DATA23
D2 BCM_DDR_DQ24
DDR0_DATA24
F4 BCM_DDR_DQ25
DDR0_DATA25
D1 BCM_DDR_DQ26
DDR0_DATA26
BCM_DDR_DQ27
F3
DDR0_DATA27
E3 BCM_DDR_DQ28
DDR0_DATA28
G5 BCM_DDR_DQ29
DDR0_DATA29
E2 BCM_DDR_DQ30
DDR0_DATA30
BCM_DDR_DQ31
E1
DDR0_DATA31
C P4 BCM_DDR_DQM0
DDR0_DM0
N6 BCM_DDR_DQM1
DDR0_DM1
BCM_DDR_DQM2
H5
DDR0_DM2
BCM_DDR_DQM3
H6
DDR0_DM3
P5 BCM_DDR_DQS0
DDR0_DQS0
N5 BCM_DDR_DQS1
DDR0_DQS1
BCM_DDR_DQS2
H4
DDR0_DQS2
G4 BCM_DDR_DQS3
DDR0_DQS3
J3 BCM_DDR_RASb
DDR0_RAS
H2 BCM_DDR_CASb
DDR0_CAS
H1 BCM_DDR_WEb
DDR0_WE
J4 BCM_DDR_CS0b
DDR0_CS0
BCM_DDR_CKE
M4
DDR0_CKE
N1 BCM_DDR_CLK0
DDR0_CLK0
N2 BCM_DDR_CLK0b
DDR0_CLK0
DDR_CLK_TEST
F5
TP22 TP22
DDR_CLK_TEST
U2 DDR_VREF0
DDR0_VREF0
C1 DDR_VREF1
DDR0_VREF1
R132 R132
D2.6V_BCM3560 4.99K-1% 4.99K-1%
1% 1%
R522 R522
4.99K-1% 4.99K-1%
1% 1%
R523 R523
B
C357 C357 C369 C369 4.99K-1% 4.99K-1%
1% 1%
470pF 470pF 1uF 1uF
New DDR routing rules:
------------------------------
All timing is relative the CLK/CLKb that arrive at the destination DDR SDRAM chip.
1) X = CLK/CLKb should be a matched differential pair with a length < 4"
2) Address and control should be X +/- 0.75" (or 100 ps)
3) DQS and DQM should be X +/- 0.75" (or 100 ps)
4) All DQs should match corresponding byte lane DQS/DQMs within +/- 0.20" (or 30 ps)
5) Place 22 ohm resistors for DQ and DQS bidirectional lines half-way between BCM and Memory.
A
6) Place 22 ohm resistors for CLK, ADDR, BA, DM, RAS, CAS, WE, CKE output-only lines near BCM.
7) Place DDR_VREF[2:1] resistor dividers near BCM.
8) Trace impedances should be 60 to 65 ohms
9) Route DDR_VREF[2:1] with 30-mil trace and at least 1 high quality ceramic bypass capacitor for each
connection to a device.
10) All traces should have a >= 3 to 1 spacing ratio from the reference GND/PWR layer. (e.g. 15 mil
line-to-line spacing for a 5 mil dielectric thickness)
5
4
RN33 RN33 22 22
BCM_DDR_WEb
5 4
BCM_DDR_CASb
6 3
BCM_DDR_RASb 7 2
BCM_DDR_CS0b 8 1
RN31 RN31 22 22
BCM_DDR_BA0 5 4
BCM_DDR_BA1
6 3
BCM_DDR_ADDR10
7 2
BCM_DDR_ADDR0 8 1
RN30 RN30 22 22
BCM_DDR_ADDR1
5 4
BCM_DDR_ADDR2 6 3
BCM_DDR_ADDR3 7 2
BCM_DDR_ADDR4 8 1
RN29 RN29 22 22
BCM_DDR_ADDR5 5 4
BCM_DDR_ADDR6
6 3
BCM_DDR_ADDR7 7 2
BCM_DDR_ADDR8 8 1
RN28 RN28 22 22
BCM_DDR_ADDR9 5 4
BCM_DDR_ADDR11 6 3
BCM_DDR_ADDR12 7 2
BCM_DDR_CKE
8 1
Route clocks as differential pairs
BCM_DDR_CLK0 R147 R147 22 22
BCM_DDR_CLK0b
R152 R152 22 22
RN24 RN24 22 22
BCM_DDR_DQ1 5 4
BCM_DDR_DQ3 6 3
BCM_DDR_DQ5 7 2
BCM_DDR_DQ7
8 1
RN2 RN2 22 22
BCM_DDR_DQ6
5 4
BCM_DDR_DQ4
6 3
BCM_DDR_DQ2 7 2
8 1
RN25 RN25 22 22
BCM_DDR_DQ15 5 4
BCM_DDR_DQM1 6 3
BCM_DDR_DQM0 7 2
BCM_DDR_DQ0 8 1
D2.6V_BCM3560 RN27 RN27 22 22
BCM_DDR_DQ8
5 4
BCM_DDR_DQ10 6 3
BCM_DDR_DQ12 7 2
R125 R125 BCM_DDR_DQ14 8 1
4.99K-1% 4.99K-1%
1% 1%
RN4 RN4 22 22
5 4
BCM_DDR_DQ13 6 3
BCM_DDR_DQ11
7 2
C75 C75 BCM_DDR_DQ9 8 1
470pF 470pF
RN34 RN34 22 22
BCM_DDR_DQ17
C79 C79 5 4
1uF 1uF BCM_DDR_DQ19 6 3
BCM_DDR_DQ21 7 2
BCM_DDR_DQ23
8 1
RN5 RN5 22 22
BCM_DDR_DQ22 5 4
BCM_DDR_DQ20
6 3
BCM_DDR_DQ18 7 2
8 1
RN36 RN36 22 22
BCM_DDR_DQ31 5 4
BCM_DDR_DQM3 6 3
BCM_DDR_DQM2
7 2
BCM_DDR_DQ16
8 1
RN37 RN37 22 22
BCM_DDR_DQ24
5 4
BCM_DDR_DQ26 6 3
BCM_DDR_DQ28 7 2
BCM_DDR_DQ30 8 1
RN7 RN7 22 22
5 4
BCM_DDR_DQ29
6 3
BCM_DDR_DQ27
7 2
BCM_DDR_DQ25
8 1
BCM_DDR_DQS0 R131 R131 22 22
BCM_DDR_DQS1 R135 R135 22 22
BCM_DDR_DQS2 R218 R218 22 22
BCM_DDR_DQS3 R231 R231 22 22
4
3
MEM_DDR_WEb
C100 C100
MEM_DDR_CASb
MEM_DDR_RASb C319 C319
MEM_DDR_CS0b
C351 C351
C397 C397
MEM_DDR_BA0
MEM_DDR_BA1 C406 C406
MEM_DDR_ADDR10
MEM_DDR_ADDR0 C288 C288
C255 C255
MEM_DDR_ADDR1
MEM_DDR_ADDR2
MEM_DDR_ADDR3
MEM_DDR_ADDR4
MEM_DDR_ADDR12
MEM_DDR_ADDR11
MEM_DDR_ADDR10
MEM_DDR_ADDR5 MEM_DDR_ADDR9
MEM_DDR_ADDR6 MEM_DDR_ADDR8
MEM_DDR_ADDR7 MEM_DDR_ADDR7
MEM_DDR_ADDR8 D2.6V_BCM3560 MEM_DDR_ADDR6
MEM_DDR_ADDR5
MEM_DDR_ADDR4
MEM_DDR_ADDR3
MEM_DDR_ADDR9 MEM_DDR_ADDR2
MEM_DDR_ADDR11 MEM_DDR_ADDR1
MEM_DDR_ADDR12 MEM_DDR_ADDR0
MEM_DDR_CKE
MEM_DDR_BA1
MEM_DDR_BA0
R407 R407 MEM_DDR_CLK0
243 (DNI) 243 (DNI) MEM_DDR_CLK0b
MEM_DDR_CLK0 1% 1%
MEM_DDR_CLK0b
MEM_DDR_CKE
MEM_DDR_CS0b
MEM_DDR_DQ1
MEM_DDR_DQ3 MEM_DDR_RASb
MEM_DDR_DQ5 MEM_DDR_CASb
MEM_DDR_DQ7 MEM_DDR_WEb
Place these 5 resistors at
MEM_DDR_DQ6
the end of the clock lines
MEM_DDR_DQ4
MEM_DDR_DQ2
MEM_DDR_DQ15
MEM_DDR_DQM1
MEM_DDR_DQM0
MEM_DDR_DQ0
MEM_DDR_DQ8
MEM_DDR_DQ10
MEM_DDR_DQ12
MEM_DDR_DQ14
MEM_DDR_DQ13
MEM_DDR_DQ11
MEM_DDR_DQ9
MEM_DDR_DQ17 MEM_DDR_ADDR12
MEM_DDR_DQ19 MEM_DDR_ADDR11
MEM_DDR_DQ21 MEM_DDR_ADDR10
MEM_DDR_DQ23 MEM_DDR_ADDR9
MEM_DDR_ADDR8
MEM_DDR_ADDR7
D2.6V_BCM3560 MEM_DDR_ADDR6
MEM_DDR_DQ22 MEM_DDR_ADDR5
MEM_DDR_DQ20 MEM_DDR_ADDR4
MEM_DDR_DQ18 MEM_DDR_ADDR3
MEM_DDR_ADDR2
MEM_DDR_ADDR1
MEM_DDR_ADDR0
MEM_DDR_DQ31 MEM_DDR_BA1
MEM_DDR_DQM3 MEM_DDR_BA0
MEM_DDR_DQM2
MEM_DDR_DQ16
R470 R470 MEM_DDR_CLK0
243 (DNI) 243 (DNI) MEM_DDR_CLK0b
1% 1%
MEM_DDR_DQ24
MEM_DDR_DQ26 MEM_DDR_CKE
MEM_DDR_DQ28
MEM_DDR_DQ30
MEM_DDR_CS0b
MEM_DDR_RASb
MEM_DDR_DQ29 MEM_DDR_CASb
MEM_DDR_DQ27 MEM_DDR_WEb
MEM_DDR_DQ25
Place these 5 resistors at
the end of the clock lines
MEM_DDR_DQS0
MEM_DDR_DQS1
MEM_DDR_DQS2
MEM_DDR_DQS3
3
2
100uF 100uF
Try to place decoupling capacitors on the
10V 10V D2.6V_BCM3560
0.1uF 0.1uF
same side of the PCB as the DDR to reduce
0.01uF 0.01uF the inductance caused by using vias.
C87 C87
0.047uF 0.047uF
10uF 10uF
2700pF 2700pF
C71 C71 C256 C256
470pF 470pF D2.6V_BCM3560
0.1uF 0.1uF 470pF 470pF
1000pF 1000pF U16 U16
MT46V16M16TG-5B MT46V16M16TG-5B
TSOP66 TSOP66
Place Cap Close
17
to Memory VREF
A13/NC
42 49 DDR_VREF0
A12 VREF
41
A11
28
A10/AP
40
A9
MEM_DDR_DQ7
39 65
A8 DQ15
38 63 MEM_DDR_DQ6
A7 DQ14
37 62 MEM_DDR_DQ5
A6 DQ13
36 60 MEM_DDR_DQ4
A5 DQ12
MEM_DDR_DQ3
35 59
A4 DQ11
MEM_DDR_DQ2
32 57
A3 DQ10
31 56 MEM_DDR_DQ1
A2 DQ9
30 256Mbit 256Mbit 54 MEM_DDR_DQ0
A1 DQ8
29 13 MEM_DDR_DQ15
A0 DDR DDR DQ7
MEM_DDR_DQ14
11
DQ6
27 SDRAM SDRAM 10 MEM_DDR_DQ13
BA1 DQ5
26 8 MEM_DDR_DQ12
BA0 DQ4
16Mx16 16Mx16
7 MEM_DDR_DQ11
DQ3
MEM_DDR_DQ10
5
DQ2
45 4 MEM_DDR_DQ9
CLK DQ1
46 2 MEM_DDR_DQ8
CLK DQ0
MEM_DDR_DQS0
44 51
CKE UDQS
16 MEM_DDR_DQS1
LDQS
24 47 MEM_DDR_DQM0
CS (IN) UDM
MEM_DDR_DQM1
20
(IN) LDM
23
RAS
22
CAS
21
WE
Byte lanes swapped to optimize layout
C99 C99 100uF 100uF
Try to place decoupling capacitors on the
10V 10V D2.6V_BCM3560
C295 C295 0.1uF 0.1uF
same side of the PCB as the DDR to reduce
the inductance caused by using vias.
C286 C286 0.01uF 0.01uF
C127 C127
C396 C396 0.047uF 0.047uF
10uF 10uF
C398 C398 2700pF 2700pF
C110 C110
C349 C349 470pF 470pF D2.6V_BCM3560
0.1uF 0.1uF
C254 C254 1000pF 1000pF U26 U26
MT46V16M16TG-5B MT46V16M16TG-5B
TSOP66 TSOP66
Place Cap Close
17
A13/NC
DDR_VREF1
42 49
to Memory VREF
A12 VREF
41
A11
28
A10/AP
40
A9
MEM_DDR_DQ23
39 65
A8 DQ15
38 63 MEM_DDR_DQ22
A7 DQ14
37 62 MEM_DDR_DQ21
A6 DQ13
36 60 MEM_DDR_DQ20
A5 DQ12
MEM_DDR_DQ19
35 59
A4 DQ11
32 57 MEM_DDR_DQ18
A3 DQ10
31 56 MEM_DDR_DQ17
A2 DQ9
30 256Mbit 256Mbit 54 MEM_DDR_DQ16
A1 DQ8
MEM_DDR_DQ31
29 13
A0 DDR DDR DQ7
MEM_DDR_DQ30
11
DQ6
27 SDRAM SDRAM 10 MEM_DDR_DQ29
BA1 DQ5
26 8 MEM_DDR_DQ28
16Mx16 16Mx16
BA0 DQ4
MEM_DDR_DQ27
7
DQ3
MEM_DDR_DQ26
5
DQ2
45 4 MEM_DDR_DQ25
CLK DQ1
46 2 MEM_DDR_DQ24
CLK DQ0
44 51 MEM_DDR_DQS2
CKE UDQS
16 MEM_DDR_DQS3
LDQS
MEM_DDR_DQM2
24 47
CS (IN) UDM
MEM_DDR_DQM3
20
(IN) LDM
23
RAS
22
CAS
21
WE
PROPRIETARY
Title Title Title
<Title> <Title> <Title>
CONFIDENTIAL
Size Size Size Document Number Document Number Document Number
C C C <Doc> <Doc> <Doc>
Date: Date: Date: Tuesday, November 07, 2006 Tuesday, November 07, 2006 Tuesday, November 07, 2006
2
1
D
C
C112 C112
470pF 470pF
B
A
Rev Rev Rev
? ? ?
Sheet Sheet Sheet 12 12 12 of of of 18 18 18
1