Harman Kardon CDR2 Service Manual page 35

CDR2
➁
Pin Descriptions
No. Pin Name
1 AINR+
2 AINR-
3 VREF
4 VA
5 AGND
6 AINL+
7 AINL-
8 TST1
10 TST2
11 TST3
14 TST4
9 HPFE
12 VD
13 DGND
16
PD
17 MCLK
18 SCLK
19 LRCK
20 FSYNC
21 SDATA
I/O
I Right channel analog positive input pin
I Right channel analog negative input Pin
O Voltage Reference output pin (VA-2.6V)
Normally connected to VA with a 0.luF ceramic capacitor in
parallel with a 10uF electrolytic capacitor.
--- Analog section Analog Power Supply, +5V
--- Analog section Analog Ground
I Left channel analog positive input pin
I Left channel analog negative input pin
Test pin (Pull-down pin)
Should be left floating.
I High Pass Filter Enable pin(Pull-up pin)
"H": ON
"L": OFF
--- Digital section Digital Power Supply pin, +5V
--- Digital section Digital Ground pin
I Power Down pin
"L" brings tne device into power-down mode. Must be done
once after power-on.
I Master Clock input pin
CMODE="H" : 384fs
CMODE="L" : 256fs
I/O Serial Data Clock pin
Data is clocked out at the falling edge of SCLK.
Slave mode: 64fs clock is input usually.
Master mode: SCLK outputs a 64fs clock.
SCLK stays low during the power-down mode(PD="L").
I/O L/R Channel Clock Select pin
Slave mode: An fs clock is fed to this LRCK pin.
Master mode: LRCK output an fs clock.
LRCK goes "H" at SMODE2="L" and "L" at SMODE2='"H"
during reset when SMODE1 "H".
I/O Frame Synchronization Signal pin
Slave mode: When "H", data bits are clocked out on SDATA.
As I 2 S slave mode ignores FSYNC, it should hold "L" or "H".
Master mode: FSYNC outputs 2fs clock.
Stay low during the power-down mode(PD="L")
O Serial Data Output pin
Data are output with MSB first, in 2's complement format.
After 20 bits are output it turns to "L". It also remains "L"at a
power-down mode(PD="L").
FUNCTION
35
harman/kardon