Sharp lc-42ad5e Service Manual page 73

Pin No.
JTAG ball assignment
AE14 TDI
AC14 TMS
AF16 TCK
AF14 not TRST
AE13 TDO
DCU ball assignment
P1 DCUTRIGGERIN
P3 DCUTRIGGEROUT
Transport stream 2 ball assignment
C23 TSIN2LBYTECLK
C22 TSIN2LBYTECLKVALID
B23 TSIN2LERROR
D19 TSIN2LPACKETCLK
B18, C18, D18, C19, TSIN2LDATA[7:0]
C20, D20, C21, D21
Transport stream 1 ball assignment
P23 TSIN1BYTECLK
M24 TSIN1BYTECLKVALID
M26 TSIN1ERROR
N26 TSIN1PACKETCLK
K26, J25, H24, J24, L26, TSIN1DATA[7:0]
L25, L24, M23.
EMI ball assignment
L3 not EMIRAS or not CI_IORD
K1 not EMICAS or not CI_IOW
J1 not EMICSA
K3 not EMICSB
K2 not EMICSC
N4 not EMICSD
J2 not EMICSE
L2 not EMICSF
L1, N3 not EMIBE[1:0]
N1 not EMIOE or not CI_OE
N2 not EMILBA or not CI_Wea
P4 EMIWAIT not TREADY
P2 EMIRD not WR
H3, H2, G2, H4, G4, E2, EMIDATA[15:0]
E1, E3, H1, D1, D2, C2,
G3, C1, B1, A1.
D5, C5, D6, B3, A2, B2, EMIADDR[25:2]
A3, B4, A4, C6, B5, A5,
D7, C7, B6, A6, B7, A7,
D9, C9, B9, A9, B10, C11
J3 not EMIREQGNT
K4 not EMIACKREQ
L4 EMIBOOTMODE0
G1 EMISDRAMCLK
J4 EMIFLASHCLK
Programmable I/O ball assignment
W1, U4, U2, U1, R2, R1, PIO0[7:0]
T2, T1
AB4, Y2, AA1, Y1, W3, PIO1[7:0]
U3, W2, W4
AF3, AD5, AE3, AE5, PIO2[7:0]
AF2, Y3, AA3, AF1
AE18, AE4, AC16, AC12, PIO3[7:0]
AE6, AC11, AC5, AE12
AE20, AD20, AF20, PIO4[7:0]
AE19, AC17, AD18,
AD17, AF19
AC22, AF22, AD21, PIO5[7:0]
AC21, AE21, AC18,
AC20, AF21
Pin Name I/O
I
I
I
I
O
I
O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
I
O
I/O
O
O
I
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
Boundary scan test data input (5 V tolerant)
Boundary scan test mode select (5 V tolerant)
Boundary scan test clock (5 V tolerant)
Boundary scan test logic reset (5 V tolerant)
Boundary scan test data output (5 V tolerant)
External trigger input to DCU (5 V tolerant)
Signal to trigger external debug circuitry (5 V tolerant)
Transport stream bit clock (5 V tolerant)
Transport stream bit clock valid edge (5 V tolerant)
Transport stream packet error (5 V tolerant)
Transport stream packet strobe (5 V tolerant)
Transport stream data (5 V tolerant)
(TSIN2LDATA7 is used for data input in serial mode)
Transport stream bit/byte clock (5 V tolerant)
Transport stream bit/byte clock valid edge (5 V tolerant)
Transport stream packet error (5 V tolerant)
Transport stream packet strobe (5 V tolerant)
Transport stream data in (5 V tolerant)
(TSIN1DATA7 is used for data input in serial mode)
Row address strobe for SDRAM
Column address strobe for SDRAM
Peripheral chip select A
Peripheral chip select B
Peripheral chip select C
Peripheral chip select D
Peripheral chip select E
Peripheral chip select F
External device data bus byte enable. 1 bit per byte of the data bus.
External device output enable.
Flash device load burst address.
External memory device target ready indicator (5 V tolerant)
External read/write access indicator. Common to all devices.
External common data bus.
External common address bus
Bus request/grant indicator
Bus grant/request indicator (5 V tolerant)
External power-up port size indicator (5 V tolerant)
SDRAM clock
Peripheral clock
Parallel input/output pin or alternative function (5 V tolerant)
5 – 16
LC-42AD5E/RU/S
Pin Function