Sharp lc-42ad5e Service Manual page 61

2.2. IC202 (RH-iXB964WJZZQ)
2.2.1 Pin Connections and short description
Pin No. Pin Name
Clock and resets
32 NOT_RESET
15 XTAL_I
14 XTAL_O
13 VDDA_2V5
16 VDDA_2V5
Analog interface
1 RF_LEVEL
2 VDDA_2V5
3 QP
4 QM
5 VDDA_ISO
6 VDDA_2V5
7 REFP
8 REFM
9 INCM
10 IM
11 IP
12 VDDA_1.0
I2C interface
29 SDA
30 SCL
21 SDAT
20 SCLT
MPEG interface
43 D7
42 D6
40 D5
39 D4
37 D3
36 D2
35 D1
33 D0
44 CLK_OUT
46 STR_OUT
47 D/NOT_P
48 ERROR
Front end controls
18 AGC_RF
17 AGC_IF
64 TEST
27 GPIO0
49 GPIO1
60 GPIO2
59 GPIO3
58 GPIO4
57 GPIO5
54 GPIO6
53 GPIO7
52 GPIO8
61 GPIO9
23 AUX_CLK
25 CS0
26 CS1
Power supply
19, 24, 31, 38,
VDD_1V0
45, 51, 55, 62
22, 28, 34, 41,
VDD_3V3
50, 56, 63
I/O
I Hardware reset, active low
I Analog Crystal oscillator input/external clock (2.5 V)
O Analog Crystal oscillator output
— Supply Analog oscillator supply (2.5 V)
— Supply Analog PLL supply (2.5 V)
— ADC 8 input for RF level monitoring
— Analog ADC 8 supply (2.5 V)
— Positive Q analog input for baseband configuration
— Negative Q analog input for baseband configuration
— Analog ISO nwell polarization (2.5 V)
— Analog ADC 12 supply (2.5 V)
— Internal positive reference
— Internal negative reference
— Internal common mode
— Negative I analog input for IF and baseband configuration
— Positive I analog input for IF and baseband configuration
— Analog supply (1.0 V)
I/O Serial data (open drain)
I Serial clock (open drain)
I/O SDA tuner (open drain)
I SCL tuner
O Serial MPEG data or parallel MPEG data (bit 7)
O Parallel MPEG data (bit 6)
O Parallel MPEG data (bit 5)
O Parallel MPEG data (bit 4)
O Parallel MPEG data (bit 3)
O Parallel MPEG data (bit 2)
O Parallel MPEG data (bit 1)
O Parallel MPEG data (bit 0)
O MPEG byte or bit clock
O MPEG first byte sync
O MPEG data valid/parity
O MPEG packet error
I/O
RF AGC control
I/O
IF AGC control (5 V tolerant)
I/O Reserved test mode, must be grounded.
I/O General-purpose input/output port 0. Reserved test mode, must be grounded.
I/O General-purpose input/output port 1
I/O General-purpose input/output port 2 or lock indicator
I/O General-purpose input/output port 3 or lock indicator
I/O General-purpose input/output port 4
I/O General-purpose input/output port 5
I/O General-purpose input/output port 6
I/O General-purpose input/output port 7
I/O General-purpose input/output port 8. Reserved test mode, must be grounded.
I/O General-purpose input/output port 9
I/O Auxiliary clock
I Chip select LSB
I Chip select MSB
— Digital core supply (1.0 V)
— Digital I/O supply (3.3 V)
5 – 4
Pin Function
(5 V tolerant)
LC-42AD5E/RU/S