Onkyo TX-SR502E Service Manual page 45

QQ
3 7 63 1515 0
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-1
Q181: BU1924FS (RDS decoder)-1
BLOCK DIAGRAM
MUX
(4)
120k
(3)
Vref
V
DD1 (5)
Power supply
(6)
V
SS1
(12)
V
DD2
Power supply
(11)
V
SS2
TE
L 13942296513
XI
TERMINAL DESCRIPTION
Pin No. Pin name Description
1 QUAL Output terminal of demodulator quality signal.
2 RDATA Output terminal of demodulator data.
3 Vref Input terminal of reference voltage.
4 MUX Input terminal of composite signal.
5 V Analog power supply.
DD1
6 V Analog power supply.
SS1
7 V Ground.
SS3
8 CMP Input terminal of comparator.
9 T2 Input terminal for test mode.
10 T1 Input terminal for test mode.
11 V Digital power supply.
SS2
12 V Digital power supply.
DD2
13 XI Connect to oscillator.
14 XO Connect to oscillator.
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15 ---
(N.C.)
16 RCLK Output terminal of demodulator clock.
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100k
100k
anti-aliasing
filter
Analog
PLL
PLL
57kHz
1187.5Hz
RDS/ARI
Digital
Reference
clock
(13) (14)
XO
x ao
y
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8
8th Switched
capacitor filter
Bi-phase
decoder
Measurement
circuit
(10)
Q Q
3 6 7 1 3
T1
u163
.
TX-SR502/E/8250/HT-R520
2 9 9 4 2 8
V CMP
SS3
(7) (8)
comparator
RCLK
(16)
QUAL
(1)
RDATA
(2)
Differential
decoder
(9)
1 5 0 5 8 2 9 9 4
T2
m
co
9 9
2 8 9 9