Sony STR-DE845 Service Manual page 51

• DIGITAL BOARD IC1401 CXD2712R (AUDIO DSP)
Pin No.
1
2 to 5
6, 7
8
9
10
11
12
13
14
15
16 to 20
21
22
23 to 25
26
27 to 30
31
32 to 40
41
42
43 to 49
50
51
52
53 to 60
61
62 to 69
70
71
72
73
74
75
76 to 80
81
82
83 to 89
90
91
92 to 94
95
96
97
98
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Pin Name I/O
VSS3 —
Ground terminal
SOA to SOD O
Serial data output to the A/D, D/A converter
ECJ0, ECJ1 I Conditional jump input terminal (fixed at "L" in this set)
NC O
Not used (fixed at "L")
XHDWR I
Write data input from the system controller (IC1201)
XHDRD I
Read data input terminal Not used (fixed at "H")
VSS4 — Ground terminal
VDD2 —
Power supply terminal (+3.3V)
HRDY O
Ready signal output to the system controller (IC1201)
XHDCS I Chip select signal input from the system controller (IC1201)
HA0 I
Address signal input from the system controller (IC1201)
HD0 to HD4 I/O
Two-way data bus with the system controller (IC1201)
VSS5 —
Ground terminal
VDD3 — Power supply terminal (+3.3V)
HD5 to HD7 I/O
Two-way data bus with the system controller (IC1201)
XRST I
Reset signal input from the system controller (IC1201) "L": reset
FGP0 toFGP3 I/O
Data output terminal for the test
VSS6 — Ground terminal
ED0 to ED8 I/O
Two-way data bus with external RAM Not used (fixed at "L")
VSS7 —
Ground terminal
VDD4 — Power supply terminal (+3.3V)
ED9 to ED15 I/O
Two-way data bus with external RAM Not used (fixed at "L")
TEST I
Test terminal (Normally: fixed at "L")
VSS8 —
Ground terminal
VDD5 — Power supply terminal (+3.3V)
ED16 to ED23 I/O
Two-way data bus with the S-RAM (IC1402)
VSS9 —
Ground terminal
ED24 to ED31 I/O Two-way data bus with the S-RAM (IC1402)
XOE O Output enable signal output to the S-RAM (IC1402)
VSS10 —
Ground terminal
VDD6 —
Power supply terminal (+3.3V)
CAS O External RAM column address strobe signal output terminal Not used
XWE O
Write enable signal output to the S-RAM (IC1402)
RAS O
External RAM raw address strobe signal output terminal Not used
EA0 to EA4 O
Address signal output to the S-RAM (IC1402) or test data input from the S-RAM (IC1402)
VSS11 — Ground terminal
VDD7 —
Power supply terminal (+3.3V)
E5 to EA11 O
Address signal output to the S-RAM (IC1402) or test data input from the S-RAM (IC1402)
EA12 O
Address signal output to the S-RAM (IC1402)
VSS0 —
Ground terminal
EA13 to EA15 O Address signal output to the S-RAM (IC1402)
EA16 O
Address signal output terminal (for check)
TSTA I
Test data input terminal (Normally: fixed at "L")
PLDIVF I
PLL input frequency select terminal
PLDIVB O PLL input frequency select terminal
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Description
"L": 256fs "H": 128fs (fixed at "L" in this set)
"L": 768fs "H": 1024fs (fixed at "H" in this set)
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