Closed Caption System - Hitachi 36SDX88B Service Manual

58 SCLI
59 SDA2
60 SCL2
61 Vdd
62 OSCI
63
osc2
64
vss
This is the clock for IIC communication.
This is the data for IIC communication.
This is the clock for IIC communication.
Vdd +5V Input
These pins are connected to an external oscillator circuit for internal clock circuit when power-on this OSCI clock start
oscillation. 4 MHz oscillator for MPC.
GND
MICROPROCESSOR (1001)
The microprocessor used is 16-bit CPU, 144KB ROM and 5 KB RAM. Oscillator frequency is 4 MHz with two
1% interfaces. There are 2 internal sync. separators for CCD decoding.
l*C BUS
The l*C bus controller interfaces via six internal control registers.
l*C transmission from master/slave receiver, slave transmitter/receiver allows direct l*C protocol. An interrupt is
generated when transfer ends then clears to high at the next write to l%. If the UPC is the slave transmitting
and transfer ends, the clock line clears at a read of PCREC after ACK=!.
The Hardware monitors the l*C bus line so the Software can start a transfer at any time.
Through Software control the l*C bus controller can force the clock line to reset the circuit leaving the contents
of the address and clock registers the same.
CLOSED CAPTION SYSTEM
The closed caption decodification is made by an algorithm of the Micon 1C. The CCD data captioning
algorithm utilizes sampling of the composite video signal during line 21. In order for the CCD algorithm
to recognize CCD burst (seven clock cycles of 503khz) certain timing relationship between incoming
composite video signal and horizontal flyback pulse (FBP) should be maintained. This algorihm determines
the display position, screen display (Roll-Up, Pop-On, Paint-On), format and character attributes (color
italics, underline, and flash).
18.5 +/- 1 .Ous
10.5 +/- 1 .ous
4
CCD
SIGNAL
1
I I
i-4 I
FBP=lO.Sus
I
h
I I
I4
l.Ous
I
I
F
I I
I
I I
Fig. 3.2.i Optimal Timing for CCD Data
Capture Algorithm.
96