Hitachi 36SDX88B Service Manual page 100

4. 3b+L
This pin is the clock input for the Bi-directional Mode,
and is used to synchronize data transfer to and from
the device. It is also used as the signaling input to switch
the device from the Transmit-Only Mode to the Bi-
directional Mode. It must remain high for the chip to
continue operation in the Transmit-Only Mode.
3. VCLK
This pin is the clock input for the Transmit-Only Mode
(ODCI). In the Transmit-Only Mode, each bit is clocked
out on the rising edge of this signal. In the Bi-directional
Mode, a high logic level is required on this pin to enable
write capability.
2.0 FUNCTIONAL DESCRIPTION
The 24LC21A is designed to comply to the DDC
Standard proposed by VESA (Figure 4-2) with the
exception that it is not access bus capable. It operates
in two modes, the Transmit-Only Mode and the Bi-
directional Mode. There is a separate 2-wire protocol
to support each mode, each having a separate clock
input but sharing a common data line (SDA). The device
enters the Transmit-Only Mode upon power-up. In this
mode, the device transmits data bits on the SDA pin in
response to a clock signal on the VCLK pin. The device
will remain in this mode until a valid high to low transition
is placed on the SCL input. When a valid transition on
SCL is recognized, the device will switch into the Bi-
directional Mode and look for its control byte to be sent
by the master. If it detects its control byte, it will stay in
the Bi-directional Mode. Otherwise, it will revert to the
Transmit-Only Mode after it sees 128 VCLK pulses.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only Mode at
address OOH. This mode supports a undirectional 2-
wire protocol for continuous transmission of the contents
of the memory array. This device requires that it be
initialized prior to valid data being sent in the Transmit-
Only Mode (Section 2.2). In this mode, data is transmitted
on the SDA pin in 8-bit bytes, with each byte followed
by a ninth, null bit. The clock source for the Transmit-
Only Mode is provided on the VCLK pin, and a data bit
is output on the rising edge on this pin. The eight bits
in each byte are transmitted most significant bit first.
Each byte within the memory array will be output in
sequence. After address 7Fh in the memory array is
transmitted. the internal address pointers will wrap
around to the first memory location (OOh) and continue.
The Bi-Directional Mode Clock (SCL) pin must be held
high for the device. to remain in the Transmit-Only Mode.
2.2 Initialization Procedure
After Vcc has stabilized, the device will be in the
Transmit-Only Mode. Nine clock cycles on the VCLK
pin must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit in address
OOh.
3.0 BI-DIRECTIONAL MODE
Before the 24LC21A can be switched into the Bi-
directional Mode it must enter the transition mode, which
is done by applying a valid high to low transition on the
Bi-directional Mode Clock (SCL). As soon it enters the
transition mode, it looks for a control byte 1010 000X
on the 12CTM bus, and starts to count pulses on VCLK.
Any high to low transition on the SCL line will reset the
count. If it sees a pulse count of 128 on VCLK while
the SC1 line is idle, it will revert back to the transmit-
Only Mode, and transmit its contents starting with the
most significant bit in address OOh. However, if it detects
the control byte on the IeTM bus, it will switch in the Bi-
directional Mode. Once the device has made the
transition to the Bi-directional mode, the only way to
switch the device back to the Transmit-Only Mode is to
remove power from the device.
Once the device has switched into the Bi-directional
Mode, the VCLK input is disregarded, with the exception
that a logic high level is required to enable write capability.
This mode supports a two-wire Bi-directional data
transmission protocol (12CTM). In this protocol, a device
that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be
cont:olled by a master device that generates the Bi-
directonal Mode Clock (SCL), controls access to the
bus and generates the START and STOP conditions,
while the 24LC21A acts as the slave. Both master and
slave can operate as transmitter or receiver, but the
master device determines which mode is activated. In
the Bi-directional mode, the 24LC21A only responds to
commands for device 1010 000X.
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