HP 98770 CE Handbook page 61

98770 Diagrams 9-11
Mnemonic
Description
Mnemonic
Description
ABL
Alpha Blanking
LXA
Load X Address
AS Alpha Select
LXC
Load X Cursor Position
AVC Address Valid Clear
LYA Load Y Address
BADR B Address Lines
LYC
Load Y
CUTsor
Position
unv
Diue Aipha VIdeo
ivii VIdeo
Video Uata hom Memory 1
BGV Blue Graphics Video
M2 Video Video Data From Memory 2
BLKG
Blinkino
M3 Video
Video Data From Memory 3
BR Bus Request MC
BV Blue Video
MSO
Memory Select Line 0
BVD Blue Video Data
MSI
Memory Select Line 1
C80
80T~
Character
MSYNC
Memory Synchronization
CAS
Column /\ddr€5S Strobe
NCS N
COUU(t:!T
St:!ied
CEBG Chained External Bus Grant
NL
New Line
CL NP New Page
COLOR Color Select Lines
NW
New Word
CRT CRT Status Line
NWE New Word Enable
CURS Cursor
OC Output Clock
CSTM Internal Start Memory Cycle
OL Output Latch
DO
Memory Data Out Lines
OS
Output Strobe
DOUT Data Out
PA Peripheral Address Lines
DMAR Direct Memory Access Request
PBR Peripheral Bus Request
DSP Display
PEBG Peripheral External Bus Grant
EBG External Bus Grant PSMC
Peripheral Synchronous Memory Complete
tOL End of Line
RAS Row Address Strobe
FB Full Brightness
RAV Red Alpha Video
FLB Full Lme Buffer RGV Red Graphics Video
FLG
Flag
RNP
Reset New Page
GAV Green Alpha Video
ROW Row Select
RV Red Video
GGV Green Graphics Video
RVD Red Video Data
GS Graphics Select
GV
Green Video
SCM
Store Color Mask
GVD
Green Video Data
SGD Select Graphics Display
HIGH Highlight Select Lines
SLT Select Line Type
SMC Store Memory Control
HLT Halt
STM
Start Memory
HSYNC Horizontal Svnchronization
STS
Status
ICI Register Select line 1
TCK
Buffered Mainframe Clock
IC2
Register Select line 2
IDA Instruction, Data. Address Bus Lines
UL Underline
INlT
Initialize
VGC
Vector Generator Clock
INT Interrupt
VBusy
Vector Generator Busv
10SB
Input / Output Strobe
V Ready Vector Point Ready
IRH High Level Interrupt
V SYNC
Vertical Synchronization
IRQ Interrupt Request
IS Input Strobe WE Write Enable Lines
LDA Load Address
WW Write Word
LEP
Load End Point XADR X Memory Address Lines
LlOD Latched 100 Bus Lines {Internal)
YADR Y Memory Address Lines
LTE Line Type Enable
YSCAN
Y Timmg Chain Output Lines
I