LG 65UG8709 Service Manual page 65

Clock for URSA9
LM14_URSA9_crystalcap
XIN_URSA
XO_URSA
SPI Flash
+3.3V_NORMAL
OPT
IC1900
NLASB3157DFT2G
B1 SELECT
1 6 FRC_FLASH_SEL
SPI_DO_URSA9
SPI_DI_URSA9
GND VCC
2 5
B0 A
3 4
SPI_DO_SOC SPI_DO
0 R1900
High : B1
Low : B0
SPI_4MB_MACRONIX
CS
OPT
SPI_CZ_URSA9
R1901
10K
SO/SIO1
R1904 33
SPI_DO
WP/SIO2
1K
R1905
FLASH_WP_URSA
OPT
GND
1K
R1932
FRC_FLASH_WP
Debugging for URSA9
I2C_S Port
P1905
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG_Wafer
1
2
R1922
33
3
SCL2_+3.3V_DB
URSA_DEBUG_Wafer
R1921 33
4
SDA2_+3.3V_DB
URSA_DEBUG_Wafer
5
SW1902
JS2235S
1 6
I2C_SCL7 I2C_SDA7
R1958 R1959
0 0
URSA_MP
URSA_MP
2 5
I2CS_SCL
I2CS_SDA
R1960 URSA_DEBUG_SW R1961
0 0
OPT OPT
3 4
SCL2_+3.3V_DB SDA2_+3.3V_DB
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
URSA Reset
+3.3V_NORMAL
SW1901
+3.3V_NORMAL
JTP-1127WEM
OPT
1 2
C1996
OPT
22uF
R1919
3 4 10V 10K
0
R1924
OPT
0
R1930
0
R13221
+3.3V_NORMAL
OPT
IC1902
NLASB3157DFT2G
B1 SELECT
1 6 FRC_FLASH_SEL
SPI_CK_URSA9
GND VCC
2 5
B0 A
3 4
SPI_DI_SOC SPI_DI
SPI_CK_SOC
0 R1920
SPI_4MB_Winbond
IC1901-*1
W25Q32FVSSIG
+3.3V_NORMAL
CS VCC
1 8
IC1901
DO[IO1] HOLD_OR_RESET[IO3]
2 7
MX25L3235E WP[IO2] CLK
3 6
GND DI[IO0]
4 5
VCC
C1995
1 8
0.1uF
16V
HOLD/SIO3
2 7
10K R1903
SCLK
3 6 SPI_CK
SI/SIO0
4 5
SPI_DI
UART PQ/System Debug
+3.3V_NORMAL
URSA9_PQ_DEBUG
P1906
R13226
12507WS-04L
10K
URSA9_PQ_DEBUG
1
2
R13222
33
3
URSA_UART2_RX
URSA9_PQ_DEBUG
33 R13223
4
URSA_UART2_TX
URSA9_PQ_DEBUG
5
C1998
0.1uF
16V
URSA9_PQ_DEBUG
Chip Config
Debug/ISP ADDR
Slave (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3'd7:111:boot from SPI Flash
+3.3V_NORMAL
URSA_RESET OPT
R1908
10K
R1902
URSA_RESET_SoC
OPT
R1907
10K
R1991
URSA_RESET_MICOM
OPT
URSA_EMI URSA_EMI URSA_EMI
R1906
10K
C1900 C1901 C1902
R1990
0.01uF 0.01uF 0.01uF
25V 25V 25V
+3.3V_NORMAL
OPT
IC1903
NLASB3157DFT2G
URSA_RESET
B1 SELECT
1 6 FRC_FLASH_SEL
GND VCC
2 5 XIN_URSA
B0 A XO_URSA
3 4
SPI_CK
0 R1926
I2CS_SDA
I2CS_SCL
Near URSA9 on forth layer
URSA_UART2_TX
URSA_Noise_KR_US
URSA_UART2_RX
URSA_UART1_TX
URSA_Noise_KR_US
SPI_CZ_URSA9
SPI_CK_URSA9
SPI_DI_URSA9
SPI_DO_URSA9
URSA_UART1_RX
URSA_Noise_KR_US
Near URSA9 on forth layer
+3.3V_NORMAL
URSA9_SYS_DEBUG
P1907
12507WS-04L R13227
10K
URSA9_SYS_DEBUG
1
2
R13224
33
3 URSA_UART1_RX
URSA9_SYS_DEBUG
33
R13225
4 URSA_UART1_TX
URSA9_SYS_DEBUG
5
C1997
0.1uF
16V
URSA9_SYS_DEBUG
URSA9 Option
DIV_BIT [1/0] MODULE DIVISION
0/0 NON DIVISION
0/1 2 DIVISION
URSA_OPT_6
1/0 4 DIVISION
1/1 8 DIVISION
URSA_OPT_5
DIV_BIT0
HIGH:URSA_PRINT_OFF DIV_BIT1
URSA_OPT_4
DIM0
LOW:URSA_PRINT_ON
URSA_OPT_4
URSA_OPT_0
10K
URSA_OPT_1
BIT [2/1/0] Tx Lane
DIM1 URSA_BIT0
0/0/0 4K@120 (16lane)
10K URSA_BIT1
0/0/1 4k@60 (8lane)
URSA_BIT2
0/1/0 5k@120 (20lane)
DIM2 0/1/1 OLED ULTRA HD
1/0/0 FHD@120 (4lane)
10K
1/0/1 FHD@60 (2lane)
1/1/0 Reserved
1/1/1 Reserved
IC2500
LGE7411(URSA9)
AF29
RESET I2C_HSC_SDA/VSYNC_LIKE2
I2C_HSC_SCL/VSYNC_LIKE3
R3
XTALO
R4
XTALI SPI1_CK/PWM2/GPIO58
SPI1_DI/PWM3/GPIO59
AJ24
I2CS_SDA SPI2_CK/PWM0/GPIO56
AH24
AR13201
33 I2CS_SCL SPI2_DI/PWM1/GPIO57
C1990 C1991
47pF 47pF
SPI3_CK/DIM10/GPIO54
50V
50V
AH26
OPT OPT
I2CM_SDA SPI3_DI/DIM11/GPIO55
AG24
I2CM_SCL/VSYNC_LIKE1 SPI4_CK/DIM8/GPIO52
SPI4_DI/DIM9/GPIO53
B4
GPIO[0][UART2_TX]
A4
URSA_Noise_KR_US
GPIO[1][UART2_RX] VSYNC_LIKE/PWM5/GPIO40
C13000 C13001
0.01uF 0.01uF
B5
GPIO[2][UART1_TX]
A5
GPIO[3][UART1_RX] DIM0/GPIO[32]
C13002
0.01uF
Change pin from A5 to C4
DIM1/GPIO[33]
DIM2/GPIO[34]
R1927
AD28
0
SPI_CZ DIM3/GPIO[35]
AD30
SPI_CK DIM4/GPIO[36]
AR13200 AC31
33 SPI_DI DIM5/GPIO[37]
AD29
SPI_DO DIM6/GPIO[38]
DIM7/GPIO[39]
AE28
INT_R21/GPIO[41]
AE27
INT_R20/GPIO[42]
GPIO43/TCON0
GPIO44/TCON1
GPIO45/TCON2
C4
IRE GPIO46/TCON3
C13003
GPIO47/TCON4
0.01uF
URSA9 UART1_RX
GPIO48/TCON5
GPIO49/TCON6
AC27
GND_1 GPIO50/TCON7
AD27
GND_2
GPIO[18]/TCON8
A7
NC_1 GPIO[19]/TCON9
B6
NC_2 GPIO[20]/TCON10
B7
NC_3 GPIO[21]/TCON11
C5
NC_4 GPIO[22]/TCON12
C6
NC_5 GPIO[23]/TCON13
C7
NC_6 GPIO24/TCON14
D4
NC_7 GPIO25/TCON15
D5
NC_8
D6
NC_9
D7
NC_10
E4
NC_11
E5
NC_12
E6
NC_13
E7
NC_14
F4
NC_15 GPIO[10]/PWM_DIM_IN[0]
F5
NC_16 GPIO[11]/PWM_DIM_IN[1]
M5
NC_17
M6
NC_18
M7
NC_19
N5
NC_20
R7
NC_21
P7
NC_22
N7
NC_23
N6
NC_24
+3.3V_NORMAL
Division Type
Module Type
Rx Interface
Tx Lane
AG25
AH25
AH28
URSA_OPT_0
Module Division OPT
AJ27
DIV_BIT0
AJ29
DIV_BIT1
AF27
URSA_OPT_4
URSA_L/D_ctrl
AG28
R132001 33
L/D_CLK
URSA_L/D_ctrl
AH27 R132002 33
URSA_Noise_KR_US
L/D_DI
C13204
AG27
C13206
5pF
5pF
URSA_OPT_5 URSA_Noise_KR_US
50V
AG26 50V
URSA_OPT_6
URSA_L/D_ctrl
AF28
R13203 33
URSA_Noise_KR_US
L/D_VSYNC
C13205
5pF
50V
AG23
+3.3V_NORMAL
DIM0
AG20
DIM1
OPT
AH23 R13204
DIM2 10K
AH20
URSA_EMI
AG21
C1912
URSA_OPT_1
R13205
0.01uF
AH22
10K
25V
URSA_BIT0
AG22
URSA_BIT1
AH21
URSA_BIT2
A3
B3
A2
C3
B2
B1
C2
C1
AG4
AG5
AH4
AH5
AH6
AJ4
AJ5
Data_Format_1
AJ6
Data_Format_0
URSA_EMI URSA_EMI
C1908 C1910
AH16
0.01uF 0.01uF
GPIO[4]
25V 25V
AG16
GPIO[5]
Y5
GPIO[6]
Y4
GPIO[7] Near URSA9 on forth layer
AB4
GPIO[8]
AB5 URSA_Noise_KR_US
URSA_Noise_KR_US For DFT JIG
GPIO[9] C13004
C13005
AG17
0.01uF
0.01uF R13206 R13209
100K 100K
AH17
AG18 R13201-*1
10K R13201
0.01uF
GPIO[12]
OPT 25V
AJ20
R13200
10K URSA9_Vx1_RX_HTPD_GPIO
URSA_Noise_KR_US
GPIO[13]
OPT
AH18
R13200-*1
URSA9_CONNECT
GPIO[14] 0.01uF
AG19
25V
GPIO[15] LOCKAn_OSD
URSA_Noise_KR_US
AH19
GPIO[16] LOCKAn_Video
AJ21
FLASH_WP_URSA
GPIO[17]
C1904 C1903
0.01uF 0.01uF
25V C13202 25V
0.01uF
URSA_EMI
URSA_EMI
25V C13203
0.01uF
25V
URSA_Noise_KR_US URSA_Noise_KR_US
BSD-14Y-UD-132-HD
2013.12.17
LGE Internal Use Only